IP Library › Granted Patent US 7,564,126
Granted Patent B2
US 7,564,126 · App. 11/206,229 · Granted Jul 21, 2009

Integrated circuit package

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Quick Facts
Patent No.
US 7,564,126
App. No.
11/206,229
Granted
Jul 21, 2009
Kind
B2
Abstract

An integrated circuit package comprising: an substrate having a first main surface and a second main surface which are opposite to each other; a first plurality of external terminals disposed on the first main surface of said interconnection substrate; and a second plurality of external terminals disposed on the second main surface of said interconnection substrate; wherein said second plurality of external terminals comprises a predefined selection of shared external terminals defining a first interface for an integrated circuit memory package having type NAND or type NOR memory.

Claims (1352)

1. An integrated circuit package comprising:

an interconnection substrate including an ASIC integrated circuit and having a first main surface and a second main surface which are opposite to each other;

a first plurality of external terminals disposed on the first main surface of said interconnection substrate; and

a second plurality of external terminals disposed on the second main surface of said interconnection substrate;

wherein said second plurality of external terminals comprises a predefined selection of external terminals defining a first interface for another integrated circuit memory package disposed on said first interface and having either type NAND memory or type NOR memory;

wherein said selection of external terminals of the first interface includes shared external terminals that are used by both the type NAND memory and the type NOR memory;

wherein said second plurality of external terminals comprises another predefined selection of external terminals defining a second interface for said other integrated circuit memory package disposed on said second interface and further having type 32-bit DDR SDRAM memory.

2. The integrated circuit package according to claim 1 , wherein said ASIC integrated circuit package and said integrated circuit memory package constitute a package-on-package type integrated circuit package.

3. The integrated circuit package according to claim 1 , wherein said first plurality of external terminals define a third interface for a printed circuit board.

4. The integrated circuit package according to claim 1 , wherein said shared external terminals are defined according to TABLE 1:

TABLE 1

External terminal

External terminal

coordinate

NAND interface

NOR interface

description

U2

I/O 0

ADQ 0

Address/Data

U1

I/O 1

ADQ 1

Address/Data

V2

I/O 2

ADQ 2

Address/Data

V1

I/O 3

ADQ 3

Address/Data

AA3

I/O 4

ADQ 4

Address/Data

AA4

I/O 5

ADQ 5

Address/Data

Y3

I/O 6

ADQ 6

Address/Data

Y4

I/O 7

ADQ 7

Address/Data

R1

I/O 8

ADQ 8

Address/Data

T1

I/O 9

ADQ 9

Address/Data

N1

I/O 10

ADQ 10

Address/Data

P2

I/O 11

ADQ 11

Address/Data

P1

I/O 12

ADQ 12

Address/Data

M1

I/O 13

ADQ 13

Address/Data

J2

I/O 14

ADQ 14

Address/Data

K2

I/O 15

ADQ 15

Address/Data

AA8

/CE0

/CE0mm

Chip enable

W1

/CE1

/CE1mm

Chip enable

Y10

R/B0

RDY0

Ready output

Y8

R/B1

RDY1

Ready output

AA9

ALE

AVD

Address valid

K1

/WE

/WEmm

Write enable

L2

/RE

/OE

Output enable

AA5

/RESET

/RESET

HW reset pin

T2

Vcc

Vcc

Power supply

AA6

Vccq

Vccq

Data out power

M2

Vss

Vssmm

Ground

R2

Vss

Vssmm

Ground

Y6

Vss

Vssmm

Ground.

5. The integrated circuit package according to claim 1 , wherein said another predefined selection of external terminals is defined according to TABLE 4:

TABLE 4

External terminal

DDR SDRAM

External terminal

coordinate

interface

description

B13

/CLKd

System differential

clock

A12

CLKd

System differential

clock

T21

/CS0

Chip select

T20

/CS1

Chip select

G20

A0

Address input

K20

A1

Address input

J20

A2

Address input

J21

A3

Address input

U21

A4

Address input

R20

A5

Address input

M21

A6

Address input

M20

A7

Address input

N20

A8

Address input

K21

A9

Address input

Y16

A10

Address input

N21

A11

Address input

R21

A12

Address input

AA15

A13

Address input

Y12

A14

Address input

AA18

BA0

Bank select address

V20

BA1

Bank select address

V21

/RAS

Row address strobe

U20

/CAS

Column address

strobe

Y18

/WEd

Write enable

Y15

CKE0

Clock enable

Y13

CKE1

Clock enable

H1

DQM0

Data I/O mask

A4

DQM1

Data I/O mask

A14

DQM2

Data I/O mask

A18

DQM3

Data I/O mask

C2

DQS0

Data strobe

B8

DQS1

Data strobe

B15

DQS2

Data strobe

A19

DQS3

Data strobe

E1

DQ0

Data I/O

E2

DQ1

Data I/O

G2

DQ2

Data I/O

D1

DQ3

Data I/O

G1

DQ4

Data I/O

D2

DQ5

Data I/O

B3

DQ6

Data I/O

B4

DQ7

Data I/O

B10

DQ8

Data I/O

B6

DQ9

Data I/O

A8

DQ10

Data I/O

B9

DQ11

Data I/O

A9

DQ12

Data I/O

A5

DQ13

Data I/O

B7

DQ14

Data I/O

A6

DQ15

Data I/O

A10

DQ16

Data I/O

B11

DQ17

Data I/O

B12

DQ18

Data I/O

A11

DQ19

Data I/O

A17

DQ20

Data I/O

A16

DQ21

Data I/O

B18

DQ22

Data I/O

B17

DQ23

Data I/O

C20

DQ24

Data I/O

D20

DQ25

Data I/O

C21

DQ26

Data I/O

E20

DQ27

Data I/O

B19

DQ28

Data I/O

D21

DQ29

Data I/O

G21

DQ30

Data I/O

E21

DQ31

Data I/O

P21

Vdd

Power supply

W21

Vdd

Power supply

Y14

Vdd

Power supply

AA11

Vdd

Power supply

AA14

Vdd

Power supply

AA19

Vdd

Power supply

AA17

Vdd

Power supply

P20

Vssd

Ground

W20

Vssd

Ground

P20

Vssd

Ground

Y11

Vssd

Ground

Y19

Vssd

Ground

Y17

Vssd

Ground

AA13

Vssd

Ground

AA16

Vssd

Ground

A3

Vddq

Data output power

A15

Vddq

Data output power

B16

Vddq

Data output power

B5

Vddq

Data output power

F2

Vddq

Data output power

F21

Vddq

Data output power

H21

Vddq

Data output power

J1

Vddq

Data output power

L20

Vddq

Data output power

A7

Vssq

Data output ground

A13

Vssq

Data output ground

B14

Vssq

Data output ground

C1

Vssq

Data output ground

F1

Vssq

Data output ground

F20

Vssq

Data output ground

H2

Vssq

Data output ground

H20

Vssq

Data output ground

L21

Vssq

Data output ground

AA12

Temp.sense

Temperature sensing.

6. The integrated circuit package according to claim 1 , wherein said second plurality of external terminals includes external terminals according to TABLE 7 for supporting said integrated circuit memory package disposed on said second plurality of external terminals and said interconnection substrate including the ASIC integrated circuit:

TABLE 7

External terminal

NOR

NAND

coordinate

interface

interface

A1, A2, B1, B2

NC

NC

A20, A21, B20, B21

NC

NC

Y1, Y2, AA1, AA2

NC

NC

Y20, Y21, AA20, AA21

NC

NC.

7. The integrated circuit package according to claim 1 , wherein said another predefined selection of external terminals includes external terminals grouped optimally by byte usage.

8. An integrated circuit package of type package-on-package comprising:

an ASIC integrated circuit package with an interconnection substrate including an ASIC integrated circuit and having a first main surface and a second main surface which are opposite to each other;

a first plurality of external terminals disposed on the first main surface of said interconnection substrate;

a second plurality of external terminals disposed on the second main surface of said interconnection substrate; and

an integrated circuit memory package having type 32-bit DDR SDRAM memory and disposed on said second plurality of external terminals and ASIC integrated circuit package;

wherein said second plurality of external terminals comprises a predefined selection of external terminals defining a first interface for said integrated circuit memory package disposed on said first interface and having either type NAND memory or type NOR memory;

wherein said selection of external terminals of the first interface includes shared external terminals that are used by both the type NAND memory and the type NOR memory;

wherein said second plurality of external terminals comprises another predefined selection of external terminals defining a second interface for said other integrated circuit memory package disposed on said second interface.

9. The integrated circuit package of type package-on-package according to claim 8 , wherein said shared external terminals are defined according to TABLE 1:

TABLE 1

External terminal

External terminal

coordinate

NAND interface

NOR interface

description

U2

I/O 0

ADQ 0

Address/Data

U1

I/O 1

ADQ 1

Address/Data

V2

I/O 2

ADQ 2

Address/Data

V1

I/O 3

ADQ 3

Address/Data

AA3

I/O 4

ADQ 4

Address/Data

AA4

I/O 5

ADQ 5

Address/Data

Y3

I/O 6

ADQ 6

Address/Data

Y4

I/O 7

ADQ 7

Address/Data

R1

1/O 8

ADQ 8

Address/Data

T1

I/O 9

ADQ 9

Address/Data

N1

I/O 10

ADQ 10

Address/Data

P2

I/O 11

ADQ 11

Address/Data

P1

I/O 12

ADQ 12

Address/Data

M1

I/O 13

ADQ 13

Address/Data

J2

I/O 14

ADQ 14

Address/Data

K2

I/O 15

ADQ 15

Address/Data

AA8

/CE0

/CE0mm

Chip enable

W1

/CE1

/CE1mm

Chip enable

Y10

R/B0

RDY0

Ready output

Y8

R/B1

RDY1

Ready output

AA9

ALE

AVD

Address valid

K1

/WE

/WEmm

Write enable

L2

/RE

/OE

Output enable

AA5

/RESET

/RESET

HW reset pin

T2

Vcc

Vcc

Power supply

AA6

Vccq

Vccq

Data out power

M2

Vss

Vssmm

Ground

R2

Vss

Vssmm

Ground

Y6

Vss

Vssmm

Ground.

10. The integrated circuit package of type package-on-package according to claim 8 , wherein said another predefined selection of external terminals is defined according to TABLE 4:

TABLE 4

External terminal

DDR SDRAM

External terminal

coordinate

interface

description

B13

/CLKd

System differential

clock

A12

CLKd

System differential

clock

T21

/CS0

Chip select

T20

/CS1

Chip select

G20

A0

Address input

K20

A1

Address input

J20

A2

Address input

J21

A3

Address input

U21

A4

Address input

R20

A5

Address input

M21

A6

Address input

M20

A7

Address input

N20

A8

Address input

K21

A9

Address input

Y16

A10

Address input

N21

A11

Address input

R21

A12

Address input

AA15

A13

Address input

Y12

A14

Address input

AA18

BA0

Bank select address

V20

BA1

Bank select address

V21

/RAS

Row address strobe

U20

/CAS

Column address

strobe

Y18

/WEd

Write enable

Y15

CKE0

Clock enable

Y13

CKE1

Clock enable

H1

DQM0

Data I/O mask

A4

DQM1

Data I/O mask

A14

DQM2

Data I/O mask

A18

DQM3

Data I/O mask

C2

DQS0

Data strobe

B8

DQS1

Data strobe

B15

DQS2

Data strobe

A19

DQS3

Data strobe

E1

DQ0

Data I/O

E2

DQ1

Data I/O

G2

DQ2

Data I/O

D1

DQ3

Data I/O

G1

DQ4

Data I/O

D2

DQ5

Data I/O

B3

DQ6

Data I/O

B4

DQ7

Data I/O

B10

DQ8

Data I/O

B6

DQ9

Data I/O

A8

DQ10

Data I/O

B9

DQ11

Data I/O

A9

DQ12

Data I/O

A5

DQ13

Data I/O

B7

DQ14

Data I/O

A6

DQ15

Data I/O

A10

DQ16

Data I/O

B11

DQ17

Data I/O

B12

DQ18

Data I/O

A11

DQ19

Data I/O

A17

DQ20

Data I/O

A16

DQ21

Data I/O

B18

DQ22

Data I/O

B17

DQ23

Data I/O

C20

DQ24

Data I/O

D20

DQ25

Data I/O

C21

DQ26

Data I/O

E20

DQ27

Data I/O

B19

DQ28

Data I/O

D21

DQ29

Data I/O

G21

DQ30

Data I/O

E21

DQ31

Data I/O

P21

Vdd

Power supply

W21

Vdd

Power supply

Y14

Vdd

Power supply

AA11

Vdd

Power supply

AA14

Vdd

Power supply

AA19

Vdd

Power supply

AA17

Vdd

Power supply

P20

Vssd

Ground

W20

Vssd

Ground

P20

Vssd

Ground

Y11

Vssd

Ground

Y19

Vssd

Ground

Y17

Vssd

Ground

AA13

Vssd

Ground

AA16

Vssd

Ground

A3

Vddq

Data output power

A15

Vddq

Data output power

B16

Vddq

Data output power

B5

Vddq

Data output power

F2

Vddq

Data output power

F21

Vddq

Data output power

H21

Vddq

Data output power

J1

Vddq

Data output power

L20

Vddq

Data output power

A7

Vssq

Data output ground

A13

Vssq

Data output ground

B14

Vssq

Data output ground

C1

Vssq

Data output ground

F1

Vssq

Data output ground

F20

Vssq

Data output ground

H2

Vssq

Data output ground

H20

Vssq

Data output ground

L21

Vssq

Data output ground

AA12

Temp.sense

Temperature sensing.

11. The integrated circuit package of type package-on-package according to claim 8 , wherein said another predefined selection of external terminals comprises external terminals grouped optimally by byte usage.

12. A mobile device comprising an integrated circuit package having:

an interconnection substrate including an ASIC integrated circuit and having a first main surface and a second main surface which are opposite to each other;

a first plurality of external terminals disposed on the first main surface of said interconnection substrate; and

a second plurality of external terminals disposed on the second main surface of said interconnection substrate;

wherein said second plurality of external terminals comprises a predefined selection of external terminals defining a first interface for another integrated circuit memory package disposed on said first interface and having either type NAND memory or type NOR memory;

wherein said selection of external terminals of the first interface includes shared external terminals that are used by both the type NAND memory and the type NOR memory;

wherein said second plurality of external terminals comprises another predefined selection of external terminals defining a second interface for said other integrated circuit memory package disposed on said second interface and further having type 32-bit DDR SDRAM memory.

13. The mobile device according to claim 12 , wherein said shared external terminals are defined according to TABLE 1:

TABLE 1

External terminal

External terminal

coordinate

NAND interface

NOR interface

description

U2

I/O 0

ADQ 0

Address/Data

U1

I/O 1

ADQ 1

Address/Data

V2

I/O 2

ADQ 2

Address/Data

V1

I/O 3

ADQ 3

Address/Data

AA3

I/O 4

ADQ 4

Address/Data

AA4

I/O 5

ADQ 5

Address/Data

Y3

I/O 6

ADQ 6

Address/Data

Y4

I/O 7

ADQ 7

Address/Data

R1

I/O 8

ADQ 8

Address/Data

T1

I/O 9

ADQ 9

Address/Data

N1

I/O 10

ADQ 10

Address/Data

P2

I/O 11

ADQ 11

Address/Data

P1

I/O 12

ADQ 12

Address/Data

M1

I/O 13

ADQ 13

Address/Data

J2

I/O 14

ADQ 14

Address/Data

K2

I/O 15

ADQ 15

Address/Data

AA8

/CE0

/CE0mm

Chip enable

W1

/CE1

/CE1mm

Chip enable

Y10

R/B0

RDY0

Ready output

Y8

R/B1

RDY1

Ready output

AA9

ALE

AVD

Address valid

K1

/WE

/WEmm

Write enable

L2

/RE

/OE

Output enable

AA5

/RESET

/RESET

HW reset pin

T2

Vcc

Vcc

Power supply

AA6

Vccq

Vccq

Data out power

M2

Vss

Vssmm

Ground

R2

Vss

Vssmm

Ground

Y6

Vss

Vssmm

Ground.

14. The mobile device according to claim 12 , wherein said another predefined selection of external terminals is defined according to TABLE 4:

TABLE 4

External terminal

DDR SDRAM

External terminal

coordinate

interface

description

B13

/CLKd

System differential

clock

A12

CLKd

System differential

clock

T21

/CS0

Chip select

T20

/CS1

Chip select

G20

A0

Address input

K20

A1

Address input

J20

A2

Address input

J21

A3

Address input

U21

A4

Address input

R20

A5

Address input

M21

A6

Address input

M20

A7

Address input

N20

A8

Address input

K21

A9

Address input

Y16

A10

Address input

N21

A11

Address input

R21

A12

Address input

AA15

A13

Address input

Y12

A14

Address input

AA18

BA0

Bank select address

V20

BA1

Bank select address

V21

/RAS

Row address strobe

U20

/CAS

Column address

strobe

Y18

/WEd

Write enable

Y15

CKE0

Clock enable

Y13

CKE1

Clock enable

H1

DQM0

Data I/O mask

A4

DQM1

Data I/O mask

A14

DQM2

Data I/O mask

A18

DQM3

Data I/O mask

C2

DQS0

Data strobe

B8

DQS1

Data strobe

B15

DQS2

Data strobe

A19

DQS3

Data strobe

E1

DQ0

Data I/O

E2

DQ1

Data I/O

G2

DQ2

Data I/O

D1

DQ3

Data I/O

G1

DQ4

Data I/O

D2

DQ5

Data I/O

B3

DQ6

Data I/O

B4

DQ7

Data I/O

B10

DQ8

Data I/O

B6

DQ9

Data I/O

A8

DQ10

Data I/O

B9

DQ11

Data I/O

A9

DQ12

Data I/O

A5

DQ13

Data I/O

B7

DQ14

Data I/O

A6

DQ15

Data I/O

A10

DQ16

Data I/O

B11

DQ17

Data I/O

B12

DQ18

Data I/O

A11

DQ19

Data I/O

A17

DQ20

Data I/O

A16

DQ21

Data I/O

B18

DQ22

Data I/O

B17

DQ23

Data I/O

C20

DQ24

Data I/O

D20

DQ25

Data I/O

C21

DQ26

Data I/O

E20

DQ27

Data I/O

B19

DQ28

Data I/O

D21

DQ29

Data I/O

G21

DQ30

Data I/O

E21

DQ31

Data I/O

P21

Vdd

Power supply

W21

Vdd

Power supply

Y14

Vdd

Power supply

AA11

Vdd

Power supply

AA14

Vdd

Power supply

AA19

Vdd

Power supply

AA17

Vdd

Power supply

P20

Vssd

Ground

W20

Vssd

Ground

P20

Vssd

Ground

Y11

Vssd

Ground

Y19

Vssd

Ground

Y17

Vssd

Ground

AA13

Vssd

Ground

AA16

Vssd

Ground

A3

Vddq

Data output power

A15

Vddq

Data output power

B16

Vddq

Data output power

B5

Vddq

Data output power

F2

Vddq

Data output power

F21

Vddq

Data output power

H21

Vddq

Data output power

J1

Vddq

Data output power

L20

Vddq

Data output power

A7

Vssq

Data output ground

A13

Vssq

Data output ground

B14

Vssq

Data output ground

C1

Vssq

Data output ground

F1

Vssq

Data output ground

F20

Vssq

Data output ground

H2

Vssq

Data output ground

H20

Vssq

Data output ground

L21

Vssq

Data output ground

AA12

Temp.sense

Temperature sensing.

15. The mobile device according to claim 12 , wherein said another predefined selection of external terminals comprises external terminals grouped optimally by byte usage.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 10, 2013
From: NOKIA CORPORATION
To: NOKIA INC.
Reel/Frame 030189/0381 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 10, 2013
From: NOKIA INC.
To: MEMORY TECHNOLOGIES LLC
Reel/Frame 030190/0043 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2005
From: JAURIMO, SAKU; SIPPOLA, SAKARI
To: NOKIA CORPORATION
Reel/Frame 017140/0208 →