Method of fabricating thin film transistor

1. A method of fabricating a thin film transistor comprising:

preparing an insulative substrate;

forming an amorphous silicon layer on the insulative substrate;

forming a catalyst construction on at least a portion of the amorphous silicon layer;

connecting at least one anode and at least one cathode to the catalyst construction;

delivering a predetermined amount of electric power to the anode and the cathode, wherein the delivered electric power generates joule heat in the catalyst construction, and wherein the generated joule heat heats the amorphous silicon layer to a temperature rangina from about 800 to about 1,000° C.;

crystallizing the portion of the amorphous silicon layer on which the catalyst construction is positioned using the generated joule heat; and

crystallizing a remaining portion of the amorphous silicon layer by propagating the crystallization of the portion of the amorphous silicon layer on which the catalyst construction is positioned, thereby forming a crystallized polysilicon layer.

2. The method of claim 1 , further comprising:

removing the catalyst construction after formation of the crystallized polysilicon layer; and

patterning the polysilicon layer to form a semiconductor layer.

3. The method according to claim 2 , further comprising:

positioning a gate insulating layer over an entire surface of the substrate;

positioning a gate electrode on the gate insulating layer;

positioning an interlayer insulating layer on the entire surface of the substrate;

etching the interlayer insulating layer and the gate insulating layer to form openings;

depositing a source/drain electrode layer on the entire surface of the substrate; and

patterning the source/drain electrode layer to form source/drain electrodes.

4. The method of claim 1 , wherein forming the catalyst construction comprises:

forming a photoresist layer on a portion of the amorphous silicon layer;

forming a catalyst layer over an entire surface of the amorphous silicon layer;

forming a joule heat layer over the entire surface of the amorphous silicon layer; and

removing the photoresist layer and the portions of the catalyst layer and the joule heat layer covering the photoresist layer, thereby forming the catalyst construction on a portion of the amorphous silicon layer.

5. The method of claim 4 , wherein the catalyst layer comprises a metal selected from the group consisting of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd, Pt and mixtures thereof.

6. The method of claim 4 , wherein the catalyst layer has a thickness of about 10 to about 100 Å.

7. The method of claim 4 , wherein the joule heat layer comprises a metal selected from the group consisting of Pt, Au and mixtures thereof.

8. The method of claim 1 , wherein forming the catalyst construction comprises:

forming a catalyst layer over an entire surface of the amorphous silicon layer;

forming a joule heat layer over the entire surface of the amorphous silicon layer; and

patterning the catalyst layer and the joule heat layer, thereby forming the catalyst construction.

9. The method of claim 8 , wherein the catalyst layer comprises a metal selected from the group consisting of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd, Pt and mixtures thereof.

10. The method of claim 8 , wherein the catalyst layer has a thickness of about 10 to about 100 Å.

11. The method of claim 8 , wherein the joule heat layer comprises a metal selected from the group consisting of Pt, Au and mixtures thereof.

12. The method of claim 1 , wherein the generated joule heat is linearly proportional to the delivered electric power.

13. The method of claim 4 , wherein the joule heat is generated in the joule heat layer.

14. The method according to claim 8 , wherein the joule heat is generated in the joule heat layer.

15. The method of claim 1 , wherein the length of crystallization of the polysiliconi-layer- is proportional to the delivered electric power.

16. The method of claim 1 , wherein the length of crystallization of the polysilicon layer is proportional to the length of time the polysilicon layer is exposed to the electric power.

17. The method of claim 1 , wherein a temperature of a region of the amorphous silicon layer is reversely proportional to a distance of the region from the catalyst construction.

18. The method of claim 1 , wherein a temperature of a region of the amorphous silicon layer is proportional to the delivered electric power.

19. A method of fabricating a thin film transistor comprising:

preparing an insulative substrate;

forming an amorphous silicon layer on the insulative substrate;

forming a catalyst construction on at least a portion of the amorphous silicon layer;

connecting at least one anode and at least one cathode to the catalyst construction;

delivering a predetermined amount of electric power to the anode and the cathode, wherein the delivered electric power generates joule heat in the catalyst construction ,and wherein the generated joule heat heats the amorphous silicon layer to a temperature ranging from about 800 to about 1,000° C.;

crystallizing the portion of the amorphous silicon layer on which the catalyst construction is positioned using the generated joule heat;

crystallizing a remaining portion of the amorphous silicon layer by propagating the crystallization of the portion of the amorphous silicon layer on which the catalyst construction is

positioned, thereby forming a crystallized polysilicon layer;

positioning a gate insulating layer over an entire surface of the substrate;

positioning a gate electrode on the gate insulating layer;

positioning an interlayer insulating layer on the entire surface of the substrate;

etching the interlayer insulating layer and the gate insulating layer to form openings;

depositing a source/drain electrode layer on the entire surface of the substrate; and

patterning the source/drain electrode layer to form source/drain electrodes.