IP Library Granted Patent US 7,327,510
Granted Patent B2
US 7,327,510 · App. 11/208,052 · Granted Feb 5, 2008

Process for modifying offset voltage characteristics of an interferometric modulator

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Quick Facts
Patent No.
US 7,327,510
App. No.
11/208,052
Granted
Feb 5, 2008
Kind
B2
Abstract

An interferometric modulator manufactured according to a particular set of processing parameters may have a non-zero offset voltage. A process has been developed for modifying the processing parameters to shift the non-zero offset voltage closer to zero. For example, the process may involve identifying a set of processing parameters for manufacturing an interferometric modulator that results in a non-zero offset voltage for the interferometric modulator. The set of processing parameters may then be modified to shift the non-zero offset voltage closer to zero. For example, modifying the set of processing parameters may involve modifying one or more deposition parameters used to make the interferometric modulator, applying a current (e.g., a counteracting current) to the interferometric modulator, and/or annealing the interferometric modulator. Interferometric modulators made according to the set of modified processing parameters may have improved performance and/or simpler drive schemes.

Claims (60)

1. A process development method, comprising:

identifying a set of processing parameters for manufacturing an interferometric modulator that results in a non-zero offset voltage for the interferometric modulator; and

modifying the set of processing parameters to shift the non-zero offset voltage closer to zero.

2. The method of claim 1 , wherein modifying the set of processing parameters comprises modifying a deposition parameter.

3. The method of claim 2 , wherein modifying the deposition parameter comprises modifying a deposition temperature.

4. The method of claim 3 , wherein modifying the deposition temperature comprises modifying a dielectric layer deposition temperature.

5. The method of claim 1 , wherein modifying the set of processing parameters comprises modifying an annealing temperature.

6. The method of claim 1 , wherein the set of processing parameters comprises passing a current through the interferometric modulator.

7. The method of claim 6 , wherein modifying the set of processing parameters comprises modifying the current.

8. The method of claim 7 , wherein modifying the current comprises applying a counteracting current.

9. The method of claim 8 , wherein applying the counteracting current comprises applying a high voltage pulse.

10. The method of claim 9 comprising applying the high voltage pulse for a period of about one second or less.

11. The method of claim 1 wherein modifying the set of processing parameters comprises modifying an ionization parameter.

12. The method of claim 11 , wherein modifying the ionization parameter comprises changing a group of ions incorporated into a dielectric layer.

13. The method of claim 1 , wherein modifying the set of processing parameters comprises adding a process step.

14. The method of claim 13 , wherein the added process step comprises heating the interferometric modulator.

15. The method of claim 13 , wherein the added process step comprises passing a current through the interferometric modulator.

16. The method of claim 15 , wherein the added process step comprises applying a high voltage pulse.

17. The method of claim 1 , wherein the offset voltage comprises a resting voltage potential present across two layers of the interferometric modulator.

18. The process development method of claim 1 , comprising:

identifying a first set of processing parameters for manufacturing a first interferometric modulator;

determining a first non-zero offset voltage for the first interferometric modulator manufactured by the first set of processing parameters;

modifying the first set of processing parameters to create a second set of processing parameters; and

determining a second offset voltage for a second interferometric modulator manufactured by the second set of processing parameters, the second offset voltage being closer to zero than the first offset voltage.

19. A process development method, comprising:

identifying a means for manufacturing an interferometric modulator that results in a non-zero offset voltage for the interferometric modulator; and

modifying the means for manufacturing to shift the non-zero offset voltage closer to zero.

20. The process development method of claim 19 , wherein the means for manufacturing comprises a set of processing parameters.

21. A method of modifying an interferometric modulator, comprising:

identifying an interferometric modulator having a non-zero offset voltage; and

applying a current to the interferometric modulator to thereby shift the non-zero offset voltage closer to zero.

22. The method of claim 21 , wherein applying the current comprises applying a counteracting current.

23. The method of claim 21 , wherein applying the current comprises applying a high voltage pulse.

24. The method of claim 23 , wherein the high voltage pulse is greater than about an actuation voltage of the interferometric modulator.

25. The method of claim 21 , wherein a manufacturing yield of an interferometric modulator manufacturing process is increased.

26. The method of claim 21 , wherein the current is applied by an array driver of a display device.

27. A modified interferometric modulator made by the method of claim 21 .

28. A process of manufacturing an interferometric modulator, wherein the process is developed by the method of claim 1 .

29. An interferometric modulator made by the process of claim 28 .

30. The process of claim 28 , comprising:

forming an optical stack over a substrate;

forming a sacrificial layer over the optical stack;

forming a support structure;

forming a moveable reflective layer over the sacrificial layer; and

forming a cavity.

31. An interferometric modulator made by the process of claim 30 .

32. A display device comprising the interferometric modulator of claim 31 .

33. The display device of claim 32 , further comprising:

a display;

a processor that is in electrical communication with the display, the processor being configured to process image data;

a memory device in electrical communication with the processor.

34. The display device of claim 33 , further comprising:

a driver circuit configured to send at least one signal to the display.

35. The display device of claim 34 , further comprising:

a controller configured to send at least a portion of the image data to the driver circuit.

36. The display device of claim 33 , further comprising:

an image source module configured to send said image data to said processor.

37. The display device of claim 36 , wherein the image source module comprises at least one of a receiver, transceiver, and transmitter.

38. The display device of claim 33 , further comprising:

an input device configured to receive input data and to communicate the input data to the processor.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2016
From: QUALCOMM MEMS TECHNOLOGIES, INC.
To: SNAPTRACK, INC.
Reel/Frame 039891/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2009
From: IDC,LLC
To: QUALCOMM MEMS TECHNOLOGIES, INC.
Reel/Frame 023449/0614 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2005
From: CUMMINGS, WILLIAM J.; GALLY, BRIAN J.
To: IDC, LLC
Reel/Frame 016915/0625 →