Granted Patent B2

US 7,519,875 · App. 11/208,681 · Granted Apr 14, 2009

Abstract

Claims (40)

1. A memory device comprising:

a memory array;

a redundant memory portion in the memory array;

remapping logic configured to remap a defective location in the memory array to a location in the redundant memory portion; and

output logic configured to output one or more bits associated with the remapping from the memory device, wherein said one or more bits indicate whether or not the remapping logic has remapped a defective location in the memory array to a location in the redundant memory portion.

2. The memory device of claim 1 , wherein said one or more bits correspond to bits stored in one or more respective remap registers of the remapping logic.

3. The memory device of claim 1 , wherein said one or more bits correspond to bits that describe a physical connection in the remapping logic that remaps the defective memory location to a location in the redundant memory portion.

4. The memory device of claim 1 , wherein the output logic comprises:

a first multiplexer that selects between first and second inputs, the first input corresponding to a data path over which data read from the memory array travels, the second input corresponding to an output of a remap register; and

a remapping observation control signal that controls the selections made by the multiplexer.

5. The memory device of claim 4 , further comprising:

a second multiplexer that selects between an output of a first remap register and an output of a second remap register, the second multiplexer having an output that is connected to an input of the first multiplexer, wherein the selections made by the second multiplexer are controlled by at least one address bit line used to address the memory array.

6. The memory device of claim 1 , wherein the redundant memory portion comprises one or more rows in the memory array.

7. The memory device of claim 1 , wherein the redundant memory portion comprises one or more columns in the memory array.

8. The memory device of claim 1 , wherein the redundant memory portion comprises one or more blocks in the memory array.

9. A computer system for processing memory remapping information and displaying a description of memory remapping on a display monitor, the computer system comprising:

a processor programmed to receive and process one or more bits relating to a manner in which a memory device of an integrated circuit (IC) has been remapped;

a memory element that stores code to be executed by the processor, wherein the memory element includes

remapping logic configured to remap a defective location in the memory array to a location in the redundant memory portion, and

output logic configured to output one or more bits associated with the remapping from the memory device, wherein said one or more bits indicate whether or not the remapping logic has remapped a defective location in the memory array to a location in the redundant memory portion; and

a display monitor that displays a description of a manner in which the memory device of the IC has been remapped.

10. A method for determining whether a memory device of an integrated circuit (IC) has been remapped, the method comprising:

outputting from the memory device one or more bits associated with a remapping of a location in the memory device from a defective location to a location in a redundant memory portion, wherein said one or more bits indicate whether or not the defective location in the memory array has been remapped to a location in the redundant memory portion; and

processing said one or more bits to generate a description of any remapping that has occurred.

11. The method of claim 10 , further comprising:

displaying the description of the remapping on a display monitor.

12. The method of claim 10 , wherein the outputting step comprises:

asserting a control signal that causes remapping bits to be ported out of the memory device.

13. The method of claim 12 , wherein the control signal is received at a selector input of a multiplexer, the control signal causing the multiplexer to select between first and second inputs, the first input corresponding to a data path over which data read from the memory array travels, the second input corresponding to an output of a remap register that has said one or more bits stored in it.

14. The method of claim 10 , wherein the description is an indication of whether or not remapping has occurred.

15. The method of claim 10 , wherein the description is a description of a manner in which the memory device has been remapped.

16. A computer memory device having computer program instructions stored thereon for processing one or more bits associated with remapping of a memory device, the computer memory device comprising:

a first code segment for receiving said one or more bits, said one or more bits being output from a memory device of an integrated circuit (IC), wherein said one or more bits indicate whether or not a defective location in the memory device has been remapped to a location in a redundant memory portion; and

a second code segment for processing said one or more bits to generate a description of a manner in which the memory device has been remapped.

17. The computer memory device of claim 16 , further comprising:

a third code segment for displaying the description on a display monitor.

18. The computer memory device of claim 16 , further comprising:

a third code segment for printing the description on a printer.

19. The computer memory device of claim 16 , further comprising:

a third code segment for storing said description in a system which can be accessed to compare a consistency of said description over a plurality of power cycles or remappings of the device.

Assignments (11)