Liquid crystal display and method for manufacturing the same having particular pad unit
View Patent ↗Disclosed are a liquid crystal display (LCD) and a method for manufacturing the same, in which connection stability is improved when connecting a COG, a COF, or an FPC to a driving circuit. A substrate of the LCD has a display region and a non-display region at a peripheral area thereof. Terminals are provided to electrically connect an external circuit and a circuit of the display region to ends of signal lines extended from the display region and the non-display region. A flat protective layer is formed on the terminals. A plurality of pads are respectively formed of a first contact region and a flat second contact region, and each of the pads contacts a corresponding terminal, which is formed through a pad contact hole formed on the protective layer, at the first contact region, and each of the pads is electrically connected through an anisotropic conductive resin to a terminal of the external circuit by a pressing process at the flat second contact region.
1. An array substrate comprising:
a substrate including a display region and a non-display region;
a pixel array arranged in the display region to display an image; and
a pad unit arranged in the non-display region to electrically connect an external circuit to the pixel array, the pad unit comprising:
a first contact region having a contact hole;
a second contact region adjacent to the first contact region;
a first metal layer arranged over the first contact region and the second contact region;
an insulating layer on the first metal layer, the insulating layer having a plurality of contact holes; and
a second metal layer arranged over the insulating layer and electrically connected to the first metal layer through contact holes, wherein the bump located in the second contact region, contacts a second metal layer through a plurality of conductive balls.
2. The array substrate of claim 1 , wherein the contact holes are arranged along a longitudinal direction of the pad unit.
3. The array substrate of claim 2 , wherein the contact holes are spaced apart from each other by a substantially same distance.
4. The array substrate of claim 1 , further comprising an organic layer formed on the insulating layer.
5. The array substrate of claim 1 , wherein the contact holes are farmed at both end portions of the pad unit.
6. The array substrate of claim 1 , wherein the pixel array includes a gate line and a data line.
7. The array substrate of claim 6 , wherein the pad unit is electrically connected to the gate line or the data line.
8. The array substrate of claim 1 , wherein the second metal layer is larger than the first metal layer.
9. The array substrate of claim 1 , wherein the first contact region is located at both end portions of the pad unit.
10. The array substrate of claim 1 , wherein the material of said second metal layer is ITO or IZO.