Isolated stable bias circuit
A biasing circuit is described for a radio frequency (RF) amplifier that provides a stable signal source. The described bias circuit has two or more transistors coupled in at least one feedback loop, with a buffering transistor providing the output biasing signal and buffering the feedback loops from the output of the of the biasing circuit. This arrangement provides thermal compensation, reduces fluctuations in the feedback loops that stabilize the biasing circuit, and allows for higher biasing current demand.
1 . A bias circuit comprising:
a first amplifier and a second amplifier coupled in a feedback loop; and
a third amplifier;
wherein a first terminal of the third amplifier is coupled to a first terminal of the first amplifier and a second terminal of the third amplifier is coupled to the output of the bias circuit.
2 . The bias circuit of claim 1 wherein the first, second and third amplifiers comprise one or more transistors.
3 . The bias circuit of claim 2 wherein the one or more transistors comprise one of:
Field Effect Transistors (FETs), wherein the first terminals of the first and third transistors are gate terminals; and
Bipolar Junction Transistors (BJTs), wherein the first terminals of the first and third transistors are base terminals.
4 . The bias circuit of claim 1 wherein the second terminal of the third amplifier is coupled to the output of the bias circuit through a combination of resistance and inductance.
5 . The bias circuit of claim 1 wherein the second terminal of the third amplifier is coupled to a second terminal of the first amplifier and a first terminal of the second amplifier.
6 . The bias circuit of claim 5 wherein the second terminal of the third amplifier is coupled to the second terminal of the first amplifier and the first terminal of the second amplifier through a combination of resistance and inductance.
7 . The bias circuit of claim 1 further comprising:
a voltage divider coupled to the bias circuit output.
8 . A bias circuit comprising:
a first amplifier and a second amplifier coupled in a feedback loop;
a third amplifier; and
a fourth amplifier coupled in a feedback loop with the first amplifier;
wherein a first terminal of the third amplifier is coupled to a first terminal of the fourth amplifier and a second terminal of the third amplifier is coupled to the output of the bias circuit.
9 . The bias circuit of claim 8 wherein the first, second, third and fourth amplifiers comprise one or more transistors.
10 . The bias circuit of claim 9 wherein the one or more transistors comprise one of:
Field Effect Transistors (FETs), wherein the first terminals of the first and third transistors are gate terminals; and
Bipolar Junction Transistors (BJTs), wherein the first terminals of the first and third transistors are base terminals.
11 . The bias circuit of claim 8 wherein the second terminal of the third amplifier is coupled to the output of the bias circuit through a combination of resistance and inductance.
12 . The bias circuit of claim 8 wherein the second terminal of the third amplifier is coupled to a second terminal of the first amplifier and a first terminal of the second amplifier.
13 . The bias circuit of claim 12 wherein the second terminal of the third amplifier is coupled to the second terminal of the first amplifier and the first terminal of the second amplifier through one or more of:
a resistance; and
an inductance.
14 . The bias circuit of claim 8 further comprising:
a voltage divider coupled to the bias circuit output.
15 . A method for biasing a radio frequency (RF) amplifier, said method comprising:
stabilizing a reference signal using a first feedback loop;
driving a first semiconductor device with the reference signal to provide a bias signal to the RF amplifier; and
isolating the first feedback loop from the RF amplifier through the first semiconductor device.
16 . The method of claim 15 wherein the reference signal and the bias signal are each one of:
a predetermined voltage level; and
a predetermined current level.
17 . The method of claim 15 wherein the first feedback loop comprises a second semiconductor device and third semiconductor device.
18 . The method of claim 17 further comprising:
coupling a fourth semiconductor device to the third semiconductor device to form a second feedback loop.
19 . The method of claim 15 further comprising:
dividing the voltage at the bias circuit output using passive devices.