Start/stop circuit for performance counter

1. A performance counter for tracking a number of clock cycles between occurrences of an event of interest in a multi-bit signal, the performance counter comprising:

circuitry for receiving the multi-bit signal from a bus;

logic for asserting a run signal responsive to a first occurrence of the event of interest in the multi-bit signal;

logic for deasserting the run signal responsive to a second occurrence of the event of interest in the multi-bit signal; and

logic for incrementing a count value on each clock cycle while the run signal is asserted.

2. The performance counter of claim 1 further comprising logic for generating a duration end signal in response to the second occurrence of the event of interest in the multi-bit signal.

3. The performance counter of claim 2 further comprising:

logic responsive the duration end signal for comparing the count value with a shadow value; and

logic for updating the shadow value based on results of the comparing.

4. The performance counter of claim 3 further comprising logic for selecting a mode of operation the circuit.

5. The performance counter of claim 4 wherein when a minimum mode of operation is selected, the logic for comparing activates a less than signal responsive to the count value being less than the shadow value.

6. The performance counter of claim 5 wherein the logic for updating comprises logic for replacing the shadow value with the count value responsive to activation of the less than signal.

7. The performance counter of claim 4 wherein when a maximum mode of operation is selected, the logic for comparing activates a greater than signal responsive to the count value being greater than the shadow value.

8. The performance counter of claim 7 wherein the logic for updating further comprises logic for replacing the shadow value with the count value responsive to activation of the greater than signal.

9. The performance counter of claim 1 further comprising a count register for storing the count value.

10. The performance counter of claim 3 further comprising a shadow register for storing the shadow value.

11. A performance counter for tracking a number of clock cycles between occurrences of an event of interest in a multi-bit signal, the performance counter comprising:

means for receiving the multi-bit signal from a bus;

means for asserting a run signal responsive to a first occurrence of the event of interest in the multi-bit signal;

means for deasserting the run signal responsive to a second occurrence of the event of interest in the multi-bit signal; and

means for incrementing a count value on each clock cycle while the run signal is asserted.

12. The performance counter of claim 11 further comprising means for generating a duration end signal in response to the second occurrence of the event of interest in the multi-bit signal.

13. The performance counter of claim 12 further comprising:

means responsive the duration end signal for comparing the count value with a shadow value; and

means for updating the shadow value based on results of the comparing.

14. The performance counter of claim 13 further comprising means for selecting a mode of operation of the circuit.

15. The performance counter of claim 14 wherein when a minimum mode of operation is selected, the means for comparing activates a less than signal responsive to the count value being less than the shadow value.

16. The performance counter of claim 15 wherein the means for updating comprises means for replacing the shadow value with the count value responsive to activation of the less than signal.

17. The performance counter of claim 14 wherein when a maximum mode of operation is selected, the means for comparing activates a greater than signal responsive to the count value being greater than the shadow value.

18. The performance counter of claim 17 wherein the means for updating further comprises means for replacing the shadow value with the count value responsive to activation of the greater than signal.

19. The performance counter of claim 11 further comprising a count register for storing the count value.

20. The performance counter of claim 13 further comprising a shadow register for storing the shadow value.

21. A method of tracking a number of clock cycles between occurrences of an event of interest in a multi-bit signal, the method comprising:

receiving the multi-bit signal by a performance counter;

asserting a run signal responsive to a first occurrence of the event of interest in the multi-bit signal;

deasserting the run signal responsive to a second occurrence of the event of interest in the multi-bit signal; and

incrementing a count value on each clock cycle while the run signal is asserted.

22. The method of claim 21 further comprising generating a duration end signal in response to the second occurrence of the event of interest in the multi-bit signal.

23. The method of claim 22 further comprising:

responsive the duration end signal, comparing the count value with a shadow value; and

updating the shadow value based on results of the comparing.

24. The method of claim 23 further comprising selecting a mode of operation of the circuit.

25. The method of claim 24 further comprising, when a minimum mode of operation is selected, activating a less than signal responsive to the count value being less than the shadow value.

26. The method of claim 25 wherein the updating comprises replacing the shadow value with the count value responsive to activation of the less than signal.

27. The method of claim 24 further comprising, when a maximum mode of operation is selected, activating a greater than signal responsive to the count value being greater than the shadow value.

28. The method of claim 27 wherein the updating further comprises replacing the shadow value with the count value responsive to activation of the greater than signal.

29. The method of claim 21 further comprising storing the count value in a count register.

30. The method of claim 23 further storing the shadow value in a shadow register.