IP Library Granted Patent US 8,990,547
Granted Patent B2
US 8,990,547 · App. 11/209,555 · Granted Mar 24, 2015

Systems and methods for re-ordering instructions

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,990,547
App. No.
11/209,555
Granted
Mar 24, 2015
Kind
B2
Abstract

Systems, methodologies, computer-readable media, and other embodiments associated with ordering instructions are described. One exemplary system embodiment can include an analysis logic configured to analyze executable instructions from an executable program. A re-write logic can be configured to re-order selected load instructions within the executable program based on latency times for the selected load instructions.

Claims (25)

1. A system, comprising:

an analysis logic configured to analyze executable instructions from an executable program and to identify load instructions within a clock cycle, where each load instruction has an associated latency time observed during execution of the program; and

a re-write logic configured to re-order selected load instructions within the executable program based on latency times for the selected load instructions.

2. The system of claim 1 where the re-write logic is configured to create a modified executable program from the executable program by re-ordering the selected load instructions without recompiling.

3. The system of claim 1 where the re-write logic includes a binary code re-writing tool.

4. The system of claim 1 where the analysis logic is configured to read the latency times from performance data that is collected at a run-time of the executable program on a user system to provide a customized optimization of the selected load instructions for the user system.

5. The system of claim 1 where the load instruction includes a memory read instruction.

6. The system of claim 1 where:

the analysis logic his configured to identify the selected load instructions that are within a bundle to be processed in the same clock cycle; and

the re-write logic is configured to re-order the selected load instructions within the bundle to cause a first load instruction having a greater latency time to occur before a second load instruction having a lesser latency time.

7. The system of claim 1 where the re-write logic is configured to re-order the selected load instructions in an order decreasing latency times where the selected load instructions occur consecutively in the executable program.

8. The system of claim 1 where the re-write logic is configured to re-order the selected load instructions dynamically within the executable program during a run-time of the executable program.

9. The system of claim 1 where the re-write logic is configured to re-order the selected load instructions by providing feedback to a compiler where the feedback indicates that the selected load instructions should be ordered in a selected sequence and causes the compiler to order the selected load instructions in the selected sequence.

10. . The system of claim 1 where the system is embodied as computer executable instructions.

11. A computing system, comprising:

a compiler configured to compile a source program into an executable program;

a processor configured to execute the executable program;

a performance monitoring logic configured to monitor performance data from the executing program where the performance data includes at least a latency time for load instructions within the executable program;

an analysis logic configured to identify the load instructions within a clock cycle, where each load instruction has an associated latency time that was observed during execution; and

a re-write logic configured to re-order the load instructions within the clock cycle in accordance with a decreasing order of their associated latency times.

12. The computing system of claim 11 where the load instructions include memory access instructions and where the associated latency time represents a length of time for completing each memory access instruction during run-time of the executable program.

13. The computing system of claim 11 where the re-write logic is configured to re-order the load instructions by providing feedback information to the compiler to cause the compiler to re-order the load instructions during compiling of the source code.

14. The computing system of claim 11 where the re-write logic is configured re-order the load instructions dynamically within the executing program.

15. The system of claim 1 , where the load instructions include at least a first load instruction that occurs before a second load instruction in the executable program.

16. The system of claim 15 , where the executable program is changed where the second load instruction occurs before the first load instruction.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2021
From: OT PATENT ESCROW, LLC
To: VALTRUS INNOVATIONS LIMITED
Reel/Frame 058897/0262 →
PATENT ASSIGNMENT, SECURITY INTEREST, AND LIEN AGREEMENT Recorded Jan 26, 2021
From: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP; HEWLETT PACKARD ENTERPRISE COMPANY
To: OT PATENT ESCROW, LLC
Reel/Frame 055269/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →