Combined hardware and software implementation of link capacity adjustment scheme (LCAS) in SONET (synchronous optical network) virtual concatenation (VCAT)
View Patent ↗Combined hardware and software processing is applied in an end node of the network which includes mapping/demapping and deskewing. Most of the LCAS procedure is implemented in software so that it can be modified easily. Some of the procedure is implemented in hardware to meet stringent timing requirements. In particular, the handshaking protocol is implemented in software and the procedure for actually changing of the link capacity in response to the handshaking is implemented in hardware. The hardware and software communicate via a shared memory which includes a receive packet FIFO, receive control and status registers, a transmit packet FIFO, transmit control and status registers, and a transmit time slot interchange table.
1. A method for implementing Link Capacity Adjustment Scheme (LCAS) in an end node of a communications network, comprising:
in the end node
implementing the LCAS handshaking in software;
implementing the link capacity adjustment in hardware; and
interfacing the hardware and the software via a shared memory, wherein the shared memory includes a receive packet FIFO, receive control and status registers, a transmit packet FIFO, transmit control and status registers, and a transmit time slot interchange table.
2. The method according to claim 1 , wherein:
said receive control and status registers include
receive packet available, receive overflow error, receive overflow error count, receive demap enable, and
said transmit control and status registers include
new packet marker, transmit packet write error, and transmit packet write error count.
3. The method according to claim 2 , wherein:
the new packet marker begins a two millisecond timer.
4. The method according to claim 2 , wherein:
the hardware identifies the LCAS H4 byte for each member of an LCAS enabled VCG, extracts the H4 bytes, packetizes the LCAS control packet, and checks the receive packet FIFO to see if there is enough room to store the LCAS control packet.
5. The method according to claim 4 , wherein:
if there is not enough room in the receive packet FIFO, the hardware drops the LCAS control packet, sets the receive overflow error flag, and increments the receive overflow error count.
6. The method according to claim 5 , wherein:
if there is enough room in the receive packet FIFO, the hardware writes the LCAS control packet to the receive packet FIFO, sets the receive overflow error flag, and sets a bit in the receive packet available register.
7. The method according to claim 6 , wherein:
the software reads packets from the receive packet FIFO according to the receive packet available register, and sets the receive demap enable register according to the contents of the LCAS control packet.
8. The method according to claim 1 , wherein:
the hardware accumulates bytes of a receive side LCAS control packet and writes the receive side LCAS control packet to shared memory,
the software causes a processor to read the receive side LCAS control packet from shared memory, process the receive side LCAS control packet, and write the results of processing to shared memory, and
the hardware reads the results of processing from shared memory and effects the link capacity adjustment.
9. The method according to claim 8 , wherein:
the hardware writes a transmit side LCAS control packet.
10. The method according to claim 9 , wherein:
the hardware checks receive side CRC and calculates transmit side CRC.
11. An apparatus for implementing Link Capacity Adjustment Scheme (LCAS) in an end node of a communications network, comprising:
circuitry for extracting H4 bytes and assembling receive side LCAS control packets;
a processor for executing software, the software for causing said processor to process the receive side LCAS control packets and form LCAS transmit control packets;
hardware for implementing the link capacity adjustment; and
shared memory coupling the hardware and software, wherein the shared memory includes a receive packet FIFO, receive control and status registers, a transmit packet FIFO, transmit control and status registers, and a transmit time slot interchange table.
12. The apparatus according to claim 11 , wherein:
said receive control and status registers include
receive packet available, receive overflow error, receive overflow error count, receive demap enable, and
said transmit control and status registers include
new packet marker, transmit packet write error, and transmit packet write error count.