IP Library Granted Patent US 7,590,909
Granted Patent B2
US 7,590,909 · App. 11/210,415 · Granted Sep 15, 2009

In-circuit testing system and method

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Quick Facts
Patent No.
US 7,590,909
App. No.
11/210,415
Granted
Sep 15, 2009
Kind
B2
Abstract

An in-circuit testing system comprises an integrated circuit having a tri-state control pin used for inducing a tri-state mode in the integrated circuit during a scan test of the integrated circuit for controlling a time period for outputting a value associated with the scan test.

Claims (26)

1. An in-circuit testing system, comprising:

an integrated circuit having a tri-state control pin used for inducing a tri-state mode in the integrated circuit during a scan test of the integrated circuit, said integrated circuit comprising:

an output driver of the integrated circuit adapted to be placed in the tri-state mode by the tri-state control pin, wherein output modes of the output driver are controlled by turning the output mode of the output driver between on and off at a plurality of predetermined times for predetermined time periods during the scan test to output values associated with the scan test when the output mode of the output driver is turned on.

2. The system of claim 1 , further comprising an in-circuit test fixture communicatively coupled to the tri-state control pin for controlling the time period.

3. The system of claim 1 , further comprising an in-circuit test fixture adapted to communicate a signal to the tri-state control pin to toggle the output driver of the integrated circuit between on and off output modes.

4. The system of claim 1 , further comprising an in-circuit test fixture adapted to communicate a signal to the tri-state control pin to control a duration of the time period.

5. The system of claim 1 , further comprising an in-circuit test fixture adapted to monitor a state of the integrated circuit for communicating a signal to the tri-state control pin to control the time period.

6. The system of claim 1 , wherein the tri-state control pin comprises a dedicated tri-state control pin used for applying a signal to the integrated circuit during the scan test.

7. An in-circuit testing system, comprising:

an in-circuit test fixture adapted to communicate a signal to an integrated circuit to place the integrated circuit in a tri-state mode during a scan test of the integrated circuit, said integrated circuit comprising:

an output driver of the integrated circuit adapted to be placed in the tri-state mode by the in-circuit test fixture, wherein output modes of the output driver are controlled by turning the output mode of the output driver between on and off at a plurality of predetermined times for predetermined time periods during the scan test to output values associated with the scan test when the output mode of the output driver is turned on.

8. The system of claim 7 , wherein the in-circuit test fixture is adapted to monitor a state of the integrated circuit for controlling the time period.

9. The system of claim 7 , wherein the in-circuit test fixture is adapted to cooperate with an in-circuit tester to control the time period.

10. An in-circuit testing method, comprising:

shifting scan data into an integrated circuit for a scan test of the integrated circuit;

controlling a tri-state mode of the integrated circuit; and

controlling a tri-state mode applied to an output driver of the integrated circuit, wherein output modes of the output driver are controlled by turning the output mode of the output driver between on and off at a plurality of predetermined times for predetermined time periods during the scan test to output values associated with the scan test when the output mode of the output driver is turned on.

11. The method of claim 10 , further comprising communicating a signal to the tri-state control pin of the integrated circuit to control the tri-state mode.

12. The method of claim 10 , wherein controlling the tri-state mode comprises deactivating the tri-state mode to output the value.

13. The method of claim 10 , wherein controlling the tri-state mode comprises deactivating a tri-state mode applied to the output driver of the integrated circuit to output the value.

14. The method of claim 10 , further comprising communicating a signal to a dedicated tri-state control pin of the integrated circuit to control the tri-state mode.

15. An in-circuit testing system, comprising:

an integrated circuit having logic disposed therein, the logic adapted to control application of a tri-state mode to the integrated circuit during a scan test of the integrated circuit, said integrated circuit comprising:

an output driver of the integrated circuit adapted to be placed in the tri-state mode by the logic, wherein output modes of the output driver are controlled by turning the output mode of the output driver between on and off at a plurality of predetermined times for predetermined time periods during the scan test to output values associated with the scan test when the output mode of the output driver is turned on.

16. The system of claim 15 , wherein the logic is adapted to deactivate a tri-state mode applied to the output driver of the integrated to output the value.

17. The system of claim 15 , wherein the logic is adapted to monitor a state of the integrated circuit for controlling the application of the tri-state mode.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2022
From: OT PATENT ESCROW, LLC
To: VALTRUS INNOVATIONS LIMITED
Reel/Frame 060005/0600 →
PATENT ASSIGNMENT, SECURITY INTEREST, AND LIEN AGREEMENT Recorded Jan 26, 2021
From: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP; HEWLETT PACKARD ENTERPRISE COMPANY
To: OT PATENT ESCROW, LLC
Reel/Frame 055269/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2005
From: HARTNETT, FRED
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 016927/0746 →