Method and apparatus for destroying flash memory
On command and subject to a fail-safe interlock, a signal is generated to essentially instantaneously destroy the data and/or access to data stored in a flash memory device. Subsequently, the storage memory device is tested for confirmation of destruction of the data and/or access to the data. This cycle is repeated until verification of destruction of the data and/or access to data is achieved.
1 . A method for destroying a flash memory device, said method comprising the steps of:
a) applying excessive electrical power to damage the power distribution and logic circuitry associated with the flash memory device;
b) testing the flash memory to confirm destruction; and
c) repeating steps a and b until destruction is verified upon exercise of step b.
2 . The method as set forth in claim 1 , including the step of providing an interlock to prevent inadvertent exercise of step a.
3 . A method for destroying a flash memory device, said method comprising the steps of:
a) applying reverse polarity electrical power to damage the internal connectors of power distribution and logic circuitry associated with the flash memory device;
b) attempting to command and control the flash memory device to determine operability; and
c) repeating steps a and b until destruction is verified by exercise of step b.
4 . The method set forth in claim 3 , including the step of providing an interlock to prevent inadvertent exercise of step a.
5 . A method for destroying a flash memory device, said method comprising the steps of:
a) applying a value of an electrical signal in excess of the operating parameters of the flash memory to attack and destroy the integrated circuit control signals;
b) verifying non operability of the flash memory device after exercise of step a; and
c) repeating steps a and b until verification of non operability is provided by exercise of step b.
6 . A method as set forth in claim 5 , including the step of providing an interlock to prevent inadvertent exercise of step a.
7 . Apparatus for destroying a flash memory device, said apparatus comprising in combination:
a) means for applying excessive electrical power to damage the power distribution and logic circuitry associated with the flash memory device;
b) means for testing the flash memory to confirm destruction; and
c) means for actuating said applying means and said testing means until destruction is verified.
8 . The apparatus as set forth in claim 7 , including means for providing an interlock to prevent inadvertent actuation of said applying means.
9 . Apparatus for destroying a flash memory device, said apparatus comprising in combination:
a) means for applying reverse polarity electrical power to damage the internal connectors of power distribution and logic circuitry associated with the flash memory device;
b) means for attempting to command and control the flash memory device to determine operability; and
c) means for actuating said applying means and said attempting means until destruction is verified.
10 . The apparatus as set forth in claim 9 , including means for providing an interlock to prevent inadvertent actuation of said applying means.
11 . Apparatus for destroying a flash memory device, said apparatus comprising in combination:
a) means for applying a value of an electrical signal in excess of the operating parameters of the flash memory to attack and destroy the integrated circuit control signals;
b) means for verifying non operability of the flash memory device after actuation of said applying means; and
c) means for actuating said applying means and said verifying means until verification of non operability of said flash memory device is provided.
12 . The apparatus as set forth in claim 1 1 , including means for providing an interlock to prevent inadvertent actuation of said applying means.
13 . The method as set forth in claim 1 , including the step of verifying the existence of sufficient electrical energy to effect damage to the power distribution and logic circuitry.
14 . The method as set forth in claim 13 , including the step of reverting to conventional methodology for removing data from a flash memory device in the event said step of verifying indicates a lack of sufficient energy to effect the damage.
15 . The method as set forth in claim 3 , including the step of verifying the existence of sufficient electrical energy to effect damage to the power distribution and logic circuitry.
16 . The method as set forth in claim 15 , including the step of reverting to conventional methodology for removing data from a flash memory device in the event said step of verifying indicates a lack of sufficient energy to effect the damage.
17 . The method as set forth in claim 5 , including the step of verifying the existence of sufficient electrical energy to effect damage to the power distribution and logic circuitry.
18 . The method as set forth in claim 17 , including the step of reverting to conventional methodology for removing data from a flash memory device in the event said step of verifying indicates a lack of sufficient energy to effect the damage.
19 . The apparatus as set forth in claim 7 , including means for verifying the existence of sufficient electrical energy to effect damage to the power distribution and logic circuitry.
20 . The apparatus as set forth in claim 19 , including means for reverting to conventional methodology for removing data from a flash memory device in the event said verifying means indicates a lack of sufficient energy to effect the damage.
21 . The apparatus as set forth in claim 9 , including means for verifying the existence of sufficient electrical energy to effect damage to the power distribution and logic circuitry.
22 . The apparatus as set forth in claim 21 , including means for reverting to conventional methodology for removing data from a flash memory device in the event said verifying means indicates a lack of sufficient energy to effect the damage.
23 . The apparatus as set forth in claim 11 , including means for verifying the existence of sufficient electrical energy to effect damage to the power distribution and logic circuitry.
24 . The apparatus as set forth in claim 23 , including means for reverting to conventional methodology for removing data from a flash memory device in the event said verifying means indicates a lack of sufficient energy to effect the damage.