Method of determining FET junction temperature
View Patent ↗A processor is responsive to a thermistor temperature (T th ) adjacent a FET and to a drain-to-source voltage (V DS ) of the FET. The processor stores the characteristics of the PET and a thermal model of the system hardware and uses a first set of equations to determine the temperature (T J ) at the junction of the PET in a stable region of operation where T J −T th is nearly constant. The processor is further responsive to a step change in successive measurements of V DS indicative of a lag of T th relative to T J . In this step-change region, the processor then resolves T J based upon a second set of equations.
1. A method of determining a junction temperature (T J )of a field effect transistor (FET) comprising the steps of;
measuring the temperature (T th ) adjacent to the FET,
measuring the drain-to-source voltage (V DS ) of the FET,
determining the temperature T J at the junction of the FET in a stable region of operation where T J −T th is nearly constant accordance with a first set of equations,
determining a step change in successive measurements of V DS indicative of a lag of T th relative to T J thereby rendering T th unusable in the first set of equations,
immediately determining an initial FET current I FET in response to the step change using the most recent value of R DS in accordance with I FET =V DS /R DS , and
determining the temperature T J by resolving T J based upon a second set of equations until T J −T th re-stabilizes.
2. A method as set forth in claim 1 wherein resolving T J is further defined as resolving T J as equaling T th +ΔT SS (1-e −t/τ ) when ΔT SS +T th ≧T J and resolving T J =T th +ΔT SS (e −t/τ ) when ΔT SS +T th ≦T J where τ is a constant and ΔT SS is the steady-state temperature difference between the T J and T th at the initial FET current I FET determined in accordance with ΔT SS =I FET 2 R DS θ J-th where θ J-th is a fixed value of the thermal resistance determined from a thermal model of the system.
3. A method as set forth in claim 2 wherein determining the temperature T J with a first set of equations is further defined as T J =T th +(θ J-th V DS 2 /R DS ) and R DS =m T J +R INT where m is the slope and R INT (intercept) are characteristics of the FET.
4. A method of determining the current through a field effect transistor (FET) functioning as a switch comprising the steps of;
measuring the temperature T th adjacent the junction of an FET,
measuring the drain-to-source voltage (V DS ) of the FET,
determining the temperature T J at the junction of the FET in a stable region of operation where T J −T th is nearly constant accordance with the first set of equations T J =T th +(θ J-th V DS 2 /R DS ) and R DS =m T J +R INT where θ is a fixed value of the thermal resistance determined from a thermal model of the system and m is the slope and R INT (intercept) are found in the FET data sheets from the manufacturer,
determining a step change in successive measurements of V DS indicative of a lag of T th relative to T J thereby rendering T th unusable in the foregoing equations,
immediately determining an initial FET current I FET in response to the step change using the most recent value of R DS in accordance with I FET =V DS /R DS , and
determining the current through the FET by resolving T J =T th +ΔT SS (1-e −t/τ ) when ΔT SS +T th ≧T J and resolving T J =T th +ΔT SS (e −t/τ ) when ΔT SS +T th ≦T J where τ is a constant and ΔT SS is the steady-state temperature difference between the T J and T th at the initial FET current I FET determined in accordance with ΔT SS =I FET 2 R DS θ J-th .
5. A system for determining the current through a field effect transistor (FET) comprising:
a thermistor for measuring the temperature T th adjacent the junction of the FET;
a voltage meter for measuring the drain-to-source voltage (V DS ) of the FET; and
a processor responsive to T th and V DS and for storing characteristics of the FET and a thermal model of said system for determining the temperature T J at the junction of the FET in a stable region of operation where T J −T th is nearly constant accordance with a first set of equations and responsive to a step change in successive measurements of V DS indicative of a lag of T th relative to T J thereby rendering T th unusable in said first set of equations for immediately determining an initial FET current I FET in response to the step change using the most recent value of R DS in accordance with I FET =V DS /R DS and resolving T J based upon a second set of equations and reverting to said first set of equations in response to re-stabilization of T J −T th .
6. A system as set forth in claim 5 wherein resolving T J based upon a second set of equations comprising T J =T th +ΔT SS (1-e −t/τ ) when ΔT SS +T th ≧T J and resolving T J =T th +ΔT SS (e −t/τ ) when ΔT SS +T th ≦T J where τ is a constant and ΔT SS is the steady-state temperature difference between the T J and T th at the initial FET current I FET determined in accordance with ΔT SS =I FET 2 R DS θ J-th .
7. A system as set forth in claim 6 wherein determining T J with a first set of equations comprising T J =T th +(θ J-th V DS 2 /R DS ) and R DS =m T J +R INT where θ is a fixed value of the thermal resistance determined from said thermal model of said system and m is the slope and R INT (intercept) are said characteristics of the FET.
8. A system for determining the current through a field effect transistor (FET) comprising:
a heat sink for the FET;
a thermistor for measuring the temperature T th adjacent the junction of the FET;
a voltage meter for measuring the drain-to-source voltage (V DS ) of the FET; and
a processor responsive to T th and V DS and for storing characteristics of the FET and a thermal model of said system for determining the temperature T J at the junction of the FET in a stable region of operation where T J −T th is nearly constant accordance with the equations T J =T th +(θ J-th V DS 2 /R DS ) and R DS =m T J +R INT where θ is a fixed value of the thermal resistance determined from said thermal model of said system and m is the slope and R INT (intercept) are said characteristics of the FET, and
for determining a step change in successive measurements of V DS indicative of a lag of T th relative to T J thereby rendering T th unusable in the foregoing equations, and
for immediately determining an initial FET current I FET in response to the step change using the most recent value of R DS in accordance with I FET =V DS /R DS , and
for resolving T J =T th +ΔT SS (1-e −t/τ ) when ΔT SS +T th ≧T J and resolving T j =T th +ΔT SS (e −t/τ ) when ΔT SS +T th ≦T J where τ is a constant and ΔT SS is the steady-state temperature difference between the T J and T th at the initial FET current I FET determined in accordance with ΔT SS =I FET 2 R DS θ J-th .
9. A method of determining a junction temperature (J T ) of a field effect transistor (FET) comprising the steps of:
measuring the temperature (T th ) adjacent to the FET,
measuring the drain-to-source voltage (V DS ) of the FET,
analyzing successive measurements of V DS to determine whether the FET is operating in a stable region or a step-change region identified by a step change of V DS ,
determining the temperature T J when the FET is operating in the stable region in accordance with a first set of equations,
determining the temperature T J when the FET is operating in the step-change region in accordance with a second set of equations.