Integrated circuit having clock trim circuitry
View Patent ↗An integrated circuit is provided comprising a processor, an onboard system clock having a ring oscillator for generating a clock signal, a memory, and clock trim circuitry. The processor is arranged to, in response to receiving an external signal, determine the number of cycles of the clock signal during a predetermined number of cycles of the external signal or the number of cycles of the external signal during a predetermined number of cycles of the clock signal and to output the determined number of cycles to an external circuit. The processor is also arranged to, in response to receiving a trim value based on the determined number of cycles from the external circuit, store the trim value in the memory and control the clock trim circuitry to trim the frequency of the clock signal generated by the ring oscillator using the trim value.
1. An integrated circuit comprising: a processor; an onboard system clock having a ring oscillator for generating a clock signal; a memory; and clock trim circuitry, wherein the processor is arranged to:
in response to receiving an external signal, determine the number of cycles of the clock signal during a predetermined number of cycles of the external signal or the number of cycles of the external signal during a predetermined number of cycles of the clock signal and to output the determined number of cycles to an external circuit; and
in response to receiving a trim value based on the determined number of cycles from the external circuit, store the trim value in the memory and control the clock trim circuitry to trim the frequency of the clock signal generated by the ring oscillator using the trim value.
2. An integrated circuit according to claim 1 , wherein the memory incorporates non-volatile memory.
3. An integrated circuit according to claim 2 , where the non-volatile memory is flash RAM.
4. An integrated circuit according to claim 1 , wherein the clock trim circuitry incorporates a register, the processor being arranged to loading the trim value from the memory into register.
5. An integrated circuit according to claim 1 , wherein the trim value is stored permanently in the integrated circuit.
6. An integrated circuit according to claim 1 , further comprising at least one fuse, the processor being arranged to blow the at least one fuse upon outputting the determined number of cycles to the external circuit, thereby preventing the subsequently received and stored trim value from being changed.
7. An integrated circuit according to claim 1 , further comprising a digital to analog converter configured to convert the stored trim value to a voltage and supply the voltage to an input of the ring oscillator, thereby to control the frequency of the clock signal generated by the ring oscillator.
8. An integrated circuit according to claim 1 , wherein the integrated circuit is configured to operate under conditions in which the signal for which the number of cycles is being determined is at a considerably higher frequency than the other signal.
9. An integrated circuit according to claim 8 , configured to operate when a ratio of the number of cycles determined and the predetermined number of cycles is greater than about 2.
10. An integrated circuit according to claim 9 , wherein the ratio is greater than about 4.
11. An integrated circuit according to claim 1 , disposed in a package having an external pin for receiving the external signal.
12. An integrated circuit according to claim 11 , wherein the pin is a serial communication pin configurable for serial communication when the trim value is being set.
13. An integrated circuit according to claim 1 , wherein the trim value is also based on a compensation factor accounting for a temperature of the integrated circuit during the determination of the number of cycles.