Conserving power by reducing voltage supplied to an instruction-processing portion of a processor
View Patent ↗One embodiment of the present invention provides a system that facilitates reducing static power consumption of a processor. During operation, the system receives a signal indicating that instruction execution within the processor is to be temporarily halted. In response to this signal, the system halts an instruction-processing portion of the processor, and reduces the voltage supplied to the instruction-processing portion of the processor. Full voltage is maintained to a remaining portion of the processor, so that the remaining portion of the processor can continue to operate while the instruction-processing portion of the processor is in reduced power mode.
1. An instruction-processing system with minimal static power leakage, the instruction-processing system comprising:
a core with instruction-processing circuitry;
an area coupled to the core;
a core voltage provided to the core; and
an area voltage provided to the area;
wherein in a normal operation mode:
a clock signal to the core is active;
the core voltage is a first value;
the core is active;
the area voltage is a second value; and
the area is active;
wherein in a first power-saving mode that is exited upon receipt of an interrupt signal:
the clock signal to the core is inactive;
the core voltage is equal to or greater than the first value; and
the area voltage is equal to or greater than the second value;
wherein in a second power-saving mode that can be exited upon receipt of a signal that is not an interrupt signal:
the clock signal to the core is inactive;
the core voltage is less than the first value; and
the area voltage is equal to or greater than the second value.
2. The instruction-processing system of claim 1 , wherein the first power-saving mode can be exited upon receipt of a signal that is not an interrupt signal.
3. The instruction-processing system of claim 1 , wherein the area comprises a cache.
4. The instruction-processing system of claim 3 , wherein the area further comprises cache tags.
5. The instruction-processing system of claim 1 , wherein prior to entering the second power-saving mode, the state of the core is saved to a memory.
6. The instruction-processing system of claim 1 , wherein upon exiting the second power-saving mode, the state of the core is restored.
7. The instruction-processing system of claim 1 , wherein in the second power-saving mode, the core voltage is at zero.
8. A method for minimizing static power leakage in an instruction-processing system, wherein the instruction-processing system comprises a core with instruction-processing circuitry, an area coupled to the core, a core voltage provided to the core, and an area voltage provided to the area, the method comprising:
entering a normal operation mode by:
providing a clock signal to the core;
providing the core with a core voltage that is equal to a first value;
providing the area with an area voltage that is equal to a second value;
entering a first power-saving mode by:
disabling the clock signal to the core;
providing the core with a core voltage that is equal to or greater than the first value; and
providing the area with an area voltage that is equal to or greater than the second value;
exiting the first power-saving mode upon receipt of an interrupt signal;
entering a second power-saving mode by:
disabling the clock signal to the core;
setting the core voltage to a value less than the first value; and
providing the area with an area voltage that is equal to or greater than the second value; and
exiting the second power-saving mode upon receipt of a signal that is not an interrupt signal.
9. The method of claim 8 , further comprising exiting the first power-saving mode upon receipt of a signal that is not an interrupt signal.
10. The instruction-processing system of claim 8 , wherein the area comprises a cache.
11. The method of claim 10 , wherein the area further comprises cache tags.
12. The method of claim 8 , further comprising saving the state of the core to a memory prior to entering the second power-saving mode.
13. The method of claim 8 , further comprising restoring the state of the core upon exiting the second power-saving mode.
14. The method of claim 8 , wherein in the second power-saving mode, setting the core voltage to the value less than the first value comprises setting the core voltage to zero.
15. A computer-readable medium containing data representing an instruction-processing system with minimal static power leakage, the instruction- processing system comprising:
a core with instruction-processing circuitry;
an area coupled to the core;
a core voltage provided to the core; and
an area voltage provided to the area;
wherein in a normal operation mode:
a clock signal to the core is active;
the core voltage is a first value;
the core is active;
the area voltage is a second value; and
the area is active;
wherein in a first power-saving mode that is exited upon receipt of an interrupt signal:
the clock signal to the core is inactive;
the core voltage is equal to or greater than the first value; and
the area voltage is equal to or greater than the second value;
wherein in a second power-saving mode that can be exited upon receipt of a signal that is not an interrupt signal:
the clock signal to the core is inactive;
the core voltage is less than the first value; and
the area voltage is equal to or greater than the second value.
16. The computer-readable medium of claim 15 , wherein the first power-saving mode can be exited upon receipt of a signal that is not an interrupt signal.
17. The computer-readable medium of claim 15 , wherein the area comprises a cache.
18. The computer-readable medium of claim 17 , wherein the area further comprises cache tags.
19. The computer-readable medium of claim 15 , wherein prior to entering the second power-saving mode, the state of the core is saved to a memory.
20. The computer-readable medium of claim 15 , wherein upon exiting the second power-saving mode, the state of the core is restored.
21. The computer-readable medium stem of claim 15 , wherein in the second power-saving mode, the core voltage is at zero.