CMOS process active waveguides on five layer substrates
View Patent ↗A standard CMOS process is used to fabricate optical, optoelectronic and electronic devices at the same time on a monolithic integrated circuit. FIG. 12 shows an active waveguide formed by a standard CMOS process on a five layer substrate. The waveguide is a silicon strip loaded waveguide with a three layer core made of a silicon strip on a silicon slab with a silicon dioxide layer between the strip and slab. The active waveguide has two doped regions in the silicon slab adjacent to and on either side of the waveguide. FIG. 12 A is a table summarizing the elements of the waveguide of FIG. 12 and the CMOS transistors of FIGS. 1 and 2 , which are formed from the same materials at the same time on the same silicon substrate. In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.
1. An active waveguide on a substrate comprising:
a waveguide core comprising:
a layer of monocrystalline silicon disposed on the substrate,
a layer of a first dielectric material on the layer of monocrystalline silicon, and
a slab of monocrystalline silicon on the layer of the first dielectric material, where the slab and a silicon body of a transistor are formed from the same monocrystalline silicon on the same substrate,
a cladding comprised of a plurality of dielectric materials,
where at least one of the plurality of dielectric materials is comprised of a salicide block layer used during the fabrication of a transistor,
a plurality of doped regions in the slab of monocrystalline silicon,
where at least one of the plurality of doped regions is doped at the same time with the same dopant as a doped region in the structure of a transistor on the same substrate,
a plurality of ohmic contacts, each of which is formed in a region of the plurality of doped regions in the slab of monocrystalline silicon,
where at least one of the plurality of ohmic contacts is formed at the same time with the same material as an ohmic contact in the structure of a transistor on the same substrate, and
a plurality of conductive plugs coupling each of the plurality of ohmic contacts to at least one of a plurality of metal layers of an integrated circuit, where at least one of the plurality of conductive plugs is formed at the same time with the same material as a conductive plug coupling an ohmic contact of a transistor on the same substrate with the same one of a plurality of metal layers.
2. The active waveguide of claim 1 , wherein the substrate is comprised of a layer of silicon dioxide disposed on a layer of monocrystalline silicon.
3. The active waveguide of claim 2 , wherein the substrate,
the layer of monocrystalline silicon disposed on the substrate,
the layer of dielectric material disposed on the layer of monocrystalline silicon and
the slab of monocrystalline silicon disposed on the layer of dielectric material, comprises a wafer.
4. The light scattering element of claim 1 , wherein the layer of dielectric is comprised of silicon dioxide and is used to electrically isolate the transistor from the slab of monocrystalline silicon.
5. The light scattering element of claim 1 , wherein the cladding includes a bottom cladding comprised of the top layer of the substrate.
6. The light scattering element of claim 1 , wherein the cladding includes a layer of dielectric material formed at the same time as the sidewall passivation for the silicon body of a transistor.
7. The light scattering element of claim 1 , wherein the cladding includes a plurality of layers of dielectric material formed at the same time as a plurality of dielectric materials used as a gate spacer for a transistor.
8. The light scattering element of claim 1 , wherein the cladding includes a layer of dielectric material formed at the same time as a contact punch-through layer for a transistor.
9. The light scattering element of claim 1 , wherein the cladding includes a layer of dielectric material formed at the same time as an inter-level dielectric for a transistor.
10. The light scattering element of claims 6 , 7 , 8 or 9 , wherein the layer of dielectric material included in the cladding is selected from the group comprising: silicon dioxide, silicon oxynitride and silicon nitride.
11. The light scattering element of claim 1 , wherein at least one of the plurality of dielectric materials is selected from a group of dielectrics used at the same time to form a dielectric element of a transistor,
where the group of dielectrics comprises: a contact punch-through layer, an inter-layer dielectric film, a gate spacer, a salicide block, a dielectric spacer, a sidewall passivation film, an isolation dielectric, an oxide spacer and a field oxide.
12. The light scattering element of claim 11 , wherein thermal oxidation is used to form a sidewall passivation film,
where the sidewall passivation film is used as one of a plurality of dielectric materials for the optical waveguide and is formed at the same time as the sidewall passivation film for the body of a transistor.
13. The light scattering element of claim 1 , wherein at least one of the plurality of dielectric materials is selected from the group comprising: SiO 2 , SiCOH, SiCOF, Si 3 N 4 , SiON, BPSG and silicon-based materials including one or more of the following elements: oxygen, carbon, nitrogen, hydrogen, boron, phosphorus, fluorine and arsenic.
14. The light scattering element of claim 1 , wherein the transistor is selected from the group comprising: a CMOS transistor, a BiCMOS transistor, a bipolar junction transistor (BJT) and a junction FET (JFET) transistor.
15. The light scattering element of claim 1 , wherein the salicide block layer is used as a gate spacer during the fabrication of a transistor on the same substrate.
16. The active waveguide of claim 1 , wherein an ohmic contact is comprised of a metal silicide.
17. The active waveguide of claim 1 , wherein a conductive plug is comprised of tungsten.
18. The active waveguide of claim 1 , further comprising fabrication of a local interconnection between a pair of transistors, at the same time as fabricating a local interconnection for coupling an ohmic contact on the slab of monocrystalline silicon with an ohmic contact on a transistor.
19. The active waveguide of claim 18 , wherein the local interconnection is comprised of a material selected from the group comprising: tungsten and aluminum.