Thin film transistor array panel and method for manufacturing the same
View Patent ↗The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.
1. A thin film transistor array panel comprising:
an insulating substrate;
a gate line formed on the insulating substrate and comprising a gate electrode;
a gate insulating layer formed on the gate line;
a semiconductor layer formed on the gate insulating layer and overlapping the gate electrode;
diffusion barriers formed on the semiconductor layer;
ohmic contact layers disposed between the semiconductor layer and the diffusion barriers;
a data line crossing the gate line and comprising a source electrode partially contacting the diffusion barriers;
a drain electrode partially contacting the diffusion barriers and facing the source electrode; and
a pixel electrode electrically connected to the drain electrode,
wherein the diffusion barriers comprise silicide including nitrogen, or silicon doped with an n-type impurity and including nitrogen.
2. The thin film transistor array panel of claim 1 , wherein the diffusion barriers have a substantially same planar pattern as the ohmic contact layers.
3. The thin film transistor array panel of claim 1 , wherein the ohmic contact layers comprise the same material as the diffusion barriers except nitrogen.
4. The thin film transistor array panel of claim 1 , wherein the data line comprises first to third conductor layers, the first and third conductor layers comprising Mo or a Mo alloy, and the second conductor layer comprising Al or an Al alloy.
5. The thin film transistor array panel of claim 1 , further comprising color filters formed between the pixel electrode and the data line, and the drain electrode.
6. The thin film transistor array panel of claim 5 , further comprising a passivation layer formed between the pixel electrode and the color filters.
7. The thin film transistor array panel of claim 6 , further comprising an interlayer insulating layer formed between the color filters and the data line, drain electrode, and semiconductor layer.
8. The thin film transistor array panel of claim 1 , wherein the pixel electrode has a plurality of cutouts partitioning a pixel area into a plurality of domains.
9. The thin film transistor array panel of claim 1 , wherein the diffusion barriers have a thickness between 10 Å and 100 Å.