High-density SOI cross-point memory fabricating method

1. A method for fabricating a high-density silicon-on-insulator (SOI) cross-point memory array, the method comprising:

selectively forming a hard mask on an SOI substrate, defining memory areas, silicon (Si) active device areas, and top electrode areas;

etching to remove exposed Si surfaces;

selectively forming metal sidewalls adjacent the hard mask;

filling the memory areas with memory resistor material;

removing the hard mask, exposing the underlying Si active device areas;

forming an overlying layer of oxide;

etching the oxide to form contact holes to the Si active device areas;

forming diodes in the contact holes; and,

forming bottom electrode lines overlying the diodes.

2. The method of claim 1 wherein selectively forming a hard mask on an SOI substrate includes forming a hard mask from a material selected from the group including nitride and polysilicon.

3. The method of claim 1 wherein selectively forming metal sidewalls adjacent the hard mask includes:

isotropically depositing a metal;

anisotropically etching the metal to form the sidewalls between memory areas and Si active device areas, as well as bottom electrode lines.

4. The method of claim 3 wherein isotropically depositing the metal includes isotropically depositing a metal thickness in the range of 50 to 100 nanometers (nm); and,

wherein anisotropically etching the metal includes forming metal sidewalls and bottom electrode lines having a sidewall width in the range of 25 to 50 nm.

5. The method of claim 3 wherein etching the metal includes using a plasma etch process.

6. The method of claim 1 wherein selectively forming metal sidewalls adjacent the hard mask includes:

forming an electrode layer adjacent the hard mask; and,

interposing the electrode layer between a barrier layer and the hard mask.

7. The method of claim 6 wherein forming a barrier layer includes forming a barrier layer from a metal selected from the group including Ti, TiN, WN, and TaN.

8. The method of claim 6 wherein forming an electrode layer includes forming an electrode layer from a metal selected from the group including Ir, Pt, Au, and Ru.

9. The method of claim 1 wherein filling the memory areas with memory resistor material includes:

isotropically depositing a layer of oxide; and,

chemical mechanically polish (CMP) planarizing the oxide to the level of the hard mask;

etching the oxide from the memory area;

isotropically depositing memory resistor material; and,

CMP planarizing the memory resistor material to the level of the hard mask.

10. The method of claim 9 wherein isotropically depositing memory resistor material includes depositing memory resistor material by a process selected from the group including spin coating, sputtering, and metal organic chemical vapor deposition (MOCVD) processes.

11. The method of claim 1 wherein filling the memory areas with memory resistor material includes using a memory resistor material selected from the group including PCMO, colossal magnetoresistance (CMR), and a high temperature superconductivity (HTSC) material.

12. The method of claim 1 wherein removing the hard mask includes:

etching to remove all the hard mask, exposing the underlying Si;

photoresist masking the Si active device areas;

etching to remove the exposed Si between adjacent top electrode lines.

13. The method of claim 1 wherein selectively forming a hard mask on an SOI substrate includes forming 1F 2 geometry active device areas; and,

wherein etching the oxide to form contact holes to the Si active device areas includes:

centering the contact holes overlying the center of the Si active device areas;

forming the contact holes using 1F 2 geometry etching techniques; and,

in response to forming the contact holes, exposing the metal sidewalls adjacent the Si active device areas.

14. The method of claim 1 wherein forming diodes in the contact holes includes, forming a diode between a bottom electrode line and a memory area.

15. The method of claim 14 wherein forming a diode between the bottom electrode line and a memory area includes:

epitaxially growing Si in the contact holes;

performing a deep N+ implant;

performing a shallow P++ implant; and,

in response to the implants, forming a P++/N+ junction in the Si between a bottom electrode word line and a metal electrode sidewall adjacent a memory area.

16. The method of claim 14 wherein forming a diode between the bottom electrode line and a memory area includes:

isotropically depositing polysilicon;

performing a solid phase epitaxial growth process;

CMP planarizing the Si to the level of the oxide;

performing a deep N+ implant;

performing a shallow P++ implant; and,

in response to the implants, forming a P++/N+ junction in the Si between a bottom electrode word line and a metal electrode sidewall adjacent a memory area.

17. The method of claim 14 wherein forming a diode between the bottom electrode line and a memory area includes:

epitaxially growing Si in the contact holes;

performing a deep P+ implant;

performing a shallow N++ implant; and,

in response to the implants, forming a N++/P+ junction in the Si between a bottom electrode bit line and a metal electrode sidewall adjacent a memory area.

18. The method of claim 14 wherein forming a diode between the bottom electrode line and a memory area includes:

isotropically depositing polysilicon;

performing a solid phase epitaxial growth process;

CMP planarizing the Si to the level of the oxide;

performing a deep P+ implant;

performing a shallow N++ implant; and,

in response to the implants, forming a N++/P+ junction in the Si between a bottom electrode bit Line and a metal electrode sidewall adjacent a memory area.

19. The method of claim 14 wherein forming a diode between the bottom electrode line and the active device areas includes forming a diode between a bottom electrode line and a plurality of memory areas, through a single intervening diode.

20. The method of claim 19 wherein forming a diode between a bottom electrode line and a plurality of memory areas, through a single intervening diode includes forming a diode connected to the metal sidewall perimeters of a pair of adjacent memory areas.

21. The method of claim 20 further comprising:

forming a bottom electrode/top electrode memory array.

22. The method of claim 20 wherein the pair of adjacent memory areas form a unit memory in a cross-point memory array.