Method and system for interleaving in a parallel turbo decoder
View Patent ↗A method and system for interleaving in a parallel turbo decoder enables the use of economical dual-port memory. According to the method, an incoming coding block is divided into a plurality of sub-blocks (step 1005 ). Each sub-block is divided into a plurality of windows (step 1010 ). An inter-window shuffle is then performed within each sub-block (step 1015 ). Each window is divided into two sub-windows (step 1020 ). Then an intra-window permutation is performed within each sub-window (step 1025 ).
1. A method of interleaving in a parallel turbo decoder comprising:
dividing an incoming coding block into a plurality of sub-blocks;
dividing each sub-block into a plurality of windows;
performing an inter-window shuffle within each sub-block;
dividing each window into two sub-windows; and
performing an intra-window permutation within each sub-window.
2. The method of claim 1 wherein the incoming coding block is divided into three sub-blocks, where each sub-block corresponds to a MAP sub-decoder in the turbo decoder.
3. The method of claim 1 wherein the parallel turbo decoder is implemented in an ASIC or an FPGA device.
4. The method of claim 1 wherein the intra-window permutation within each sub-window is performed within two ports of a dual-port memory.
5. The method of claim 1 wherein the incoming coding block is divided into a variable number of sub-blocks corresponding to a variable number of sub-decoders used in the turbo decoder.
6. A system for interleaving in a parallel turbo decoder, comprising:
a decoder comprising a plurality of sub-decoders;
an interleaver/deinterleaver operatively connected to the decoder; and
a plurality of memory banks operatively connected to both the decoder and the interleaver/deinterleaver;
wherein an incoming coding block is divided by the decoder into a plurality of sub-blocks and each sub-block is divided into a plurality of windows, and the decoder, interleaver/deinterleaver and memory banks operatively perform an inter-window shuffle within each sub-block, divide each window into two sub-windows, and perform an intra-window permutation within each sub-window.
7. The system of claim 6 wherein the incoming coding block is divided into three sub-blocks, where each sub-block corresponds to a MAP sub-decoder in the turbo decoder.
8. The system of claim 6 wherein the parallel turbo decoder is implemented in an ASIC or an FPGA device.
9. The system of claim 6 wherein the intra-window permutation within each sub-window is performed within two ports of a dual-port memory.
10. The system of claim 6 wherein the incoming coding block is divided into a variable number of sub-blocks corresponding to a variable number of sub-decoders used in the turbo decoder.
11. A system for interleaving in a parallel turbo decoder comprising:
means for dividing an incoming coding block into a plurality of sub-blocks;
means for dividing each sub-block into a plurality of windows;
means for performing an inter-window shuffle within each sub-block;
means for dividing each window into two sub-windows; and
means for performing an intra-window permutation within each sub-window.