IP Library Granted Patent US 7,671,876
Granted Patent B2
US 7,671,876 · App. 11/217,559 · Granted Mar 2, 2010

Resolution scaler using a decimal part of an accumulator output as a weight for generating scaled pixel data

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Quick Facts
Patent No.
US 7,671,876
App. No.
11/217,559
Granted
Mar 2, 2010
Kind
B2
Abstract

A resolution scaler of the present invention uses a shift adder instead of a multiplier for scaling an input resolution. The resolution scaler is provided with a counter controller and a pixel scaler. The counter controller outputs a weight to the pixel scaler. The pixel scaler includes a first shift adder for outputting the first shift value by adding a plurality of first shift arguments generated by shifting the current pixel data, a second shift adder for outputting the second shift value by adding a plurality of second shift arguments generated by shifting the previous pixel data, and an adder for outputting the scaled pixel data by adding the first shift value and the second shift value.

Claims (34)

1. A resolution scaler, comprising:

a counter controller for outputting a weight adjusted by a reference clock and a coefficient; and

a pixel scaler for receiving the reference clock, the weight, and an input pixel data to output a scaled pixel data by shifting and adding the input pixel data according to a weight table,

wherein the counter controller includes:

an input counter for receiving the reference clock to thereby output an input count;

an accumulator for adding the coefficient to a cumulative value when a wait signal is not activated to thereby separately output an integer part of the cumulative value and a decimal part of the cumulative value; and

a comparator for comparing the input count with the integer part to thereby activate the wait signal when the input count and the integer part are different, and to deactivate the wait signal when the input count and the integer part are the same, and

wherein the pixel scaler includes:

a first shift adder for receiving the decimal part as the weight to thereby output a first shift value by adding a plurality of first shift arguments generated by shifting the weight to the first input pixel data;

a second shift adder for receiving a second weight to thereby output a second shift value by adding a plurality of second shift arguments generated by shifting the second weight to the second input pixel data; and

an adder for outputting the scaled pixel data by adding the first and the second shift values.

2. The resolution scaler as recited in claim 1 , wherein the pixel scaler includes:

a first input register for storing the current pixel data;

a second input register for storing the previous pixel data; and

a shift adding block for outputting the scaled pixel data by adding the first shift value obtained by shifting the current pixel data and the second shift value obtained by shifting the previous pixel data,

wherein the current pixel data and the previous pixel data are the input pixel data neighboring each other.

3. The resolution scaler as recited in claim 2 , wherein the shift adding block includes:

an adder for outputting the scaled pixel data by adding the first shift value and the second shift value,

wherein the second weight is obtained by subtracting the weight from 1.

4. The resolution scaler as recited in claim 3 , wherein the weight table contains a first shift count applied for the current pixel data and a second shift count applied for the previous pixel count.

5. A resolution scaler, comprising:

a means for outputting a weight in response to a reference clock and a coefficient; and

an input register for storing the N numbers of continuous input pixel data;

an M numbers of shift adding blocks for outputting a scaled pixel data by adding a first shift value generated by shifting a first input pixel data stored in the input register and a second shift value generated by shifting a second input pixel data stored in the input register,

wherein the first and the second input pixel data are adjacent and N and M are natural numbers,

wherein the means for outputting a weight includes:

an input counter for receiving the reference clock to thereby output an input count;

an accumulator for adding the coefficient to a cumulative value when a wait signal is not activated to thereby separately output an integer part of the cumulative value and a decimal part of the cumulative value; and

a comparator for comparing the input count with the integer part to thereby activate the wait signal when the input count and the integer part are different, and to deactivate the wait signal when the input count and the integer part are the same, and

wherein each shift adding block includes:

a first shift adder for receiving the decimal part as the weight to thereby output the first shift value by adding a plurality of first shift arguments generated by shifting the weight to the first input pixel data;

a second shift adder for receiving a second weight to thereby output the second shift value by adding a plurality of second shift arguments generated by shifting the second weight to the second input pixel data; and

an adder for outputting the scaled pixel data by adding the first and the second shift values.

6. The resolution scaler as recited in claim 5 having a relation of “resolution of the input pixel data: resolution of the scaled pixel data=N:M”.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2025
From: MAGNACHIP MIXED-SIGNAL, LTD.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 071813/0800 →
NUNC PRO TUNC ASSIGNMENT Recorded Mar 14, 2024
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: MAGNACHIP MIXED-SIGNAL, LTD.
Reel/Frame 066878/0875 →
RELEASE OF SECURITY INTEREST Recorded Aug 12, 2013
From: U.S. BANK NATIONAL ASSOCIATION
To: MAGNACHIP SEMICONDUCTOR LTD.
Reel/Frame 030988/0419 →
AFTER-ACQUIRED INTELLECTUAL PROPERTY KUN-PLEDGE AGREEMENT Recorded Feb 18, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
Reel/Frame 022277/0133 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2005
From: NOH, JAI-SEUNG
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 017003/0714 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2005
From: NOH, JAE-SEUNG
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 016952/0032 →