Panel and test method for display device
View Patent ↗A panel for a display device includes a display area and a peripheral area. The display area comprises a plurality of pixels each comprising a switching element and gate lines and data lines connected to the pixels. The peripheral area comprises a plurality of gate driving integrated circuit regions, a plurality of data driving integrated circuit regions, a plurality of repair lines disposed along the edge of the panel, connecting pads connected to both ends of the repair lines, a test line connected to at least one connecting pad, and a test pad connected to the test line. A test method for detecting disconnection of the data lines is also provided.
1. A panel for a display device comprising a display area and a peripheral area,
wherein the display area comprises:
a plurality of pixels each comprising a switching element; and
gate lines and data lines connected to the pixels, and
wherein the peripheral area comprises:
a plurality of gate driving integrated circuit regions;
a plurality of data driving integrated circuit regions;
a plurality of repair lines disposed along an edge of the panel;
connecting pads connected to first and second ends of the repair lines;
a test line connected to at least one connecting pad; and
a test pad connected to the test line, wherein, a first test signal is applied to the data lines and a second test signal is applied to the test pad such that a disconnected portion of one of the data lines represents a sum of a voltage associated with the first test signal and a voltage associated with the second test signal.
2. The panel of claim 1 , further comprising an intersecting repair line intersecting end portions of the data lines.
3. The panel of claim 2 , wherein the test line is connected to a connecting pad connected to the intersecting repair line.
4. The panel of claim 3 , wherein the second test signal is a predetermined voltage.
5. The panel of claim 4 , wherein the predetermined voltage is a common voltage.
6. The panel of claim 5 , wherein the connecting pad is formed in the gate driving integrated circuit regions and the data driving integrated circuit regions and the test pad is formed outside the gate driving integrated circuit regions.
7. A test method for a display device comprising a plurality of pixels each comprising a switching element, gate lines and data lines connected to the pixels, a plurality of gate driving integrated circuit regions, a plurality of data driving integrated circuit regions, a plurality of repair lines disposed along an edge of the panel, connecting pads connected to first and second ends of the repair lines, a test line connected to at least one connecting pad, and a test pad connected to the test line, the method comprising:
applying a first test signal to the data lines, wherein capacitances associated with the data lines are adapted to cause a disconnected portion of one of the data lines to substantially follow a first test voltage associated with the first test signal in response to the first test signal; and
applying a second test signal to the test pad to induce a charge corresponding to a second test voltage in the disconnected portion of the one of the data lines through the repair lines, wherein the disconnected portion of the one of the data lines is adapted to exhibit a voltage approximately equal to a sum of the first and second voltages in response to the second test signal.
8. The test method of claim 7 , the display device further comprising an intersecting repair line intersecting end portions of the data lines.
9. The test method of claim 8 , wherein the test line is connected to a connecting pad connected to the intersecting repair line.
10. The test method of claim 7 , wherein the first test signal is an array test voltage.
11. The test method of claim 10 , wherein the second test signal is a common voltage.