Method and system for performing digital signal processing operations in a computer system
A method and system for performing digital signal processing operations in a computer system are disclosed. Digital Signal Processing operations such as multiply and add (MADD) or multiply and subtract (MSUB) can be performed by general-purpose microprocessors. The DSP operations are directed to n-bit operands that are in m-bit registers. The register size (m) may be a multiple of the operand size (n). For example, the DSP operations may utilize 32-bit registers with 16-bit or 8-bit operands, or the DSP operations may utilize 64-bit registers with 32-bit, 16-bit, or 8-bit operands.
1 . A method for performing a digital signal processing operation, wherein the method comprises:
loading a first operand into a first location of a first register;
loading a second operand into a second location of a second register; and
multiplying the first register by the second register to produce a product.
2 . The method of claim 1 , wherein the first operand comprises 16 bits, the first register comprises 32 bits, and the first location is an upper portion of the first register.
3 . The method of claim 1 , wherein the first operand comprises 16 bits, the first register comprises 32 bits, and the first location is a lower portion of the first register.
4 . The method of claim 1 , wherein the second operand comprises 16 bits, the second register comprises 32 bits, and the second location is an upper portion of the second register.
5 . The method of claim 1 , wherein the second operand comprises 16 bits, the second register comprises 32 bits, and the second location is a lower portion of the second register.
6 . The method of claim 1 , wherein the method further comprises:
modifying a third register with the product.
7 . The method of claim 6 , wherein the modifying is adding.
8 . The method of claim 6 , wherein the modifying is subtracting.
9 . The method of claim 6 , wherein the method further comprises:
shifting the product prior to modifying the third register with the product.
10 . A system for performing a digital signal processing operation:
a first register for storing a first operand, wherein the first operand occupies a first location in the first register;
a second register for storing a second operand, wherein the second operand occupies a second location in the second register; and
a multiplier for multiplying the first register by the second register to produce a product.
11 . The system of claim 10 , wherein the first operand comprises 16 bits, the first register comprises 32 bits, and the first location is an upper portion of the first register.
12 . The system of claim 10 , wherein the first operand comprises 16 bits, the first register comprises 32 bits, and the first location is a lower portion of the first register.
13 . The system of claim 10 , wherein the second operand comprises 16 bits, the second register comprises 32 bits, and the second location is an upper portion of the second register.
14 . The system of claim 10 , wherein the second operand comprises 16 bits, the second register comprises 32 bits, and the second location is a lower portion of the second register.
15 . The system of claim 10 , wherein the system further comprises:
a left shifter for selectively shifting the product.
16 . The system of claim 10 , wherein the system further comprises:
an inverter for selectively inverting the product.
17 . The system of claim 10 , wherein the system further comprises:
an accumulator for adding a third register to the product.