Methods and apparatus for low power SRAM

1. An SRAM memory system, comprising:

at least one memory cell having a true node operatively coupled to a bit line and a complementary node operatively coupled to a complementary bit line; and

at least one write pre-charge circuit operable to charge the bit line and the complementary bit line to a voltage level below a power supply level, Vdd, of the SRAM memory prior to writing data to the at least one memory cell, wherein the at least one write pre-charge circuit:

includes at least one NMOS field effect transistor coupled from Vdd to the bit line and at least one NMOS field effect transistor coupled from Vdd to the complementary bit line, and

is operable to charge the bit line to about Vdd-Vth and to charge the complementary bit line to about Vdd-Vth, where Vth is approximately a threshold voltage of the NMOS field effect transistors.

2. The SRAM memory system of claim 1 , further comprising: at least one read pre-charge circuit operable to charge the bit line and the complementary bit line to a voltage level at about the power supply level, Vdd, of the SRAM memory prior to reading data from the at least one memory cell.

3. The SRAM memory system of claim 2 , wherein the at least one read pre-charge circuit includes at least one PMOS field effect transistor coupled from Vdd to the bit line and at least one PMOS field effect transistor coupled from Vdd to the complementary bit line.

4. The SRAM memory system of claim 1 , further comprising: at least one write buffer including at least one NMOS field effect transistor coupled from Vdd to the bit line and at least one NMOS field effect transistor coupled from Vdd to the complementary bit line.

5. The SRAM memory system of claim 4 , wherein the at least one write buffer further includes at least one NMOS field effect transistor coupled from the bit line to Vss and at least one NMOS field effect transistor coupled from the complementary bit line to Vss.

6. The SRAM memory system of claim 4 , wherein the write buffer is operable to drive the bit line to about Vdd-Vth and to drive the complementary bit line to about Vss, when the data to be written is a logic high value, where Vth is approximately a threshold voltage of the NMOS field effect transistors.

7. The SRAM memory system of claim 4 , wherein the write buffer is operable to drive the complementary bit line to about Vdd-Vth and to drive the bit line to about Vss, when the data to be written is a logic low value, where Vth is approximately a threshold voltage of the NMOS field effect transistors.

8. An SRAM memory system, comprising:

at least one memory cell having a true node operatively coupled to a bit line and a complementary node operatively coupled to a complementary bit line;

at least one write pre-charge circuit operable to charge the bit line and the complementary bit line to a voltage level below a power supply level, Vdd, of the SRAM memory prior to writing data to the at least one memory cell; and

at least one read pre-charge circuit operable to charge the bit line and the complementary bit line to about Vdd prior to reading data from the at least one memory cell,

wherein the at least one write pre-charge circuit:

includes at least one NMOS field effect transistor coupled from Vdd to the bit line and at least one NMOS field effect transistor coupled from Vdd to the complementary bit line, and

is operable to charge the bit line to about Vdd-Vth and to charge the complementary bit line to about Vdd-Vth, where Vth is approximately a threshold voltage of the NMOS field effect transistors.

9. A method of controlling an SRAM memory, comprising pre-charging a bit line and a complementary bit line of an SRAM memory cell of the SRAM memory to a voltage level below a power supply level, Vdd, of the SRAM memory prior to writing data to the memory cell, wherein the voltage level below Vdd is about Vdd-Vth, where Vth is approximately a threshold voltage of an NMOS field effect transistor.

10. The method of claim 9 , further comprising driving the bit line to about Vdd-Vth and driving the complementary bit line to about Vss, when the data to be written is a logic high value.

11. The method of claim 9 , further comprising driving the complementary bit line to about Vdd-Vth and driving the bit line to about Vss, when the data to be written is a logic low value.

12. The method of claim 9 , further comprising charging the bit line and the complementary bit line to a voltage level of about Vdd prior to reading data from the memory cell.