Resettable memory apparatuses and design
View Patent ↗Resettable memory implemented using memory without reset and methods and apparatuses to design the same. A resettable memory may include: a plurality of resettable memory cells; a plurality of memory units; and a reset information propagation logic coupled to the resettable memory cells and the memory units. The reset information propagation logic is to write reset information into a portion of the memory units when one of the resettable memory cells has a reset value and one of the memory units is written into. Alternatively, a resettable memory may include: a memory unit; a resettable finite state machine to change state in response to write request to the memory unit; and a selector coupled to the finite state machine and the memory unit to select one from a reset value and an output from the memory unit based on at least a state of the finite state machine.
1. A method to design a circuit, the method comprising:
identifying a representation of a resettable memory from a first design of the circuit; and
implementing the resettable memory to generate a second design of the circuit with a hierarchy of a first plurality of resettable memory cells and a second plurality of memory units coupled with a reset information propagation logic, the reset information propagation logic to write reset information into a third plurality of the memory units from one of the resettable memory cells having a reset value when one of the second plurality of the memory units is written into with a non-reset value.
2. The method of claim 1 , wherein, when the one of the memory units is addressed for write, the reset information propagation logic is to write in parallel reset information into all of the memory units except the one of the memory units that is addressed for write, if the one of the resettable memory cells has a reset value.
3. The method of claim 1 , wherein one or more of the memory units have no reset capability; each of the resettable memory cells is resettable to one predetermined reset value in response to a reset signal; and a reset value in the one of the resettable memory cells is cleared, after reset information is written into the portion of the memory units in response to the one of the resettable memory cells having a reset value.
4. The method of claim 1 , wherein the second design further includes a multiplexer coupled to the resettable memory cells and the memory units; when a memory location is addressed for read,
if one of the resettable memory cells that is in control of the memory location has a reset value, the multiplexer is to output a predetermined reset value, and
if one of the resettable memory cells that is in control of the memory address does not have a reset value, the multiplexer is to output a value retrieved from one of the memory units according to the memory location.
5. The method of claim 4 , wherein the second design further includes:
a plurality of memory address lines coupled to the resettable memory cells and the memory units, a first portion of the memory address lines to select an output from a selected one of the resettable memory cells and to address one addressed memory location in each of the memory units, and a second portion of the memory address lines to determine one of the memory units.
6. The method of claim 1 , wherein the first design is a behavioral level or a register transfer level design; and the second design is a gate level design.
7. A machine readable storage medium containing executable computer program instructions which when executed by a digital processing system cause said system to perform a method to design a circuit, the method comprising:
identifying a representation of a resettable memory from a first design of the circuit; and
implementing the resettable memory to generate a second design of the circuit with a hierarchy of a first plurality of resettable memory cells and a second plurality of memory units coupled with a reset information propagation logic, the reset information propagation logic to write reset information into a third plurality of the memory units from one of the resettable memory cells having a reset value when one of the second plurality of the memory units is written into with a non-reset value.
8. The storage medium of claim 7 , wherein, when the one of the memory units is addressed for write, the reset information propagation logic is to write in parallel reset information into all of the memory units except the one of the memory units that is addressed for write, if the one of the resettable memory cells has a reset value.
9. The medium of claim 7 , wherein one or more of the memory units have no reset capability; each of the resettable memory cells is resettable to one predetermined reset value in response to a reset signal; and a reset value in one of the resettable memory cells is cleared, after reset information is written into the portion of the memory units in response to the one of the resettable memory cells having a reset value; and the second design further includes: a plurality of memory address lines coupled to the resettable memory cells and the memory units, a first portion of the memory address lines to select an output from a selected one of the resettable memory cells and to address one addressed memory location in each of the memory units, and a second portion of the memory address lines to determine one of the memory units.
10. A data processing system to design a circuit, the system comprising:
means for identifying a representation of a resettable memory from a first design of the circuit; and
means for implementing the resettable memory to generate a second design of the circuit with a hierarchy of a first plurality of resettable memory cells and a second plurality of memory units coupled with a reset information propagation logic, the reset information propagation logic to write reset information into a third plurality of the memory units from one of the resettable memory cells having a reset value when one of the second plurality of the memory units is written into.
11. A data processing system to design a circuit, the data processing system comprising:
a memory to store a first design of a circuit;
a processor coupled to the memory, the processor to identify a representation of a resettable memory from a first design of the circuit, and
implementing the resettable memory to generate a second design of the circuit with a hierarchy of a first plurality of resettable memory cells and a second plurality of memory units coupled with a reset information propagation logic, the reset information propagation logic to write reset information into a third plurality of the memory units from one of the resettable memory cells having a reset value when one of the second plurality of the memory units is written into with a non-reset value.
12. The data processing system of claim 11 , wherein, when the one of the memory units is addressed for write, the reset information propagation logic is to write in parallel reset information into all of the memory units except the one of the memory units that is addressed for write, if the one of the resettable memory cells has a reset value;
wherein one or more of the memory units have no reset capability;
wherein each of the resettable memory cells is resettable to one predetermined reset value in response to a reset signal; and
wherein a reset value in the one of the resettable memory cells is cleared, after reset information is written into the portion of the memory units in response to the one of the resettable memory cells having a reset value.