CPP read sensors having constrained current paths made of lithographically-defined conductive vias and methods of making the same
View Patent ↗Current-perpendicular-to-plane (CPP) read sensors for magnetic heads having constrained current paths made of lithographically-defined conductive vias, and methods of making the same, are disclosed. In one example, a sensor stack structure which includes an electrically conductive spacer layer is formed over a first shield layer. An insulator layer is deposited over and adjacent the spacer layer, and a resist structure which exposes one or more portions of the insulator layer is formed over the insulator layer. With the resist structure in place, the exposed insulator layer portions are removed by etching to form one or more apertures through the insulator layer down to the spacer layer. Electrically conductive materials are subsequently deposited within the one or more apertures to form one or more lithographically-defined conductive vias of a current-constraining structure.
1. A method of making a current-perpendicular-to-plane (CPP) read sensor having a constrained current path, the method comprising the acts of:
forming a sensor stack structure;
performing a lithographic process to form a current-constraining structure adjacent an electrically conductive layer of the sensor stack structure, the current-constraining structure comprising a plurality of lithographically-defined conductive vias surrounded by insulator materials, the lithographic process comprising the further acts of:
forming an insulator layer over the electrically conductive layer;
forming a resist structure over the insulator layer which exposes insulator materials of the insulator layer;
etching, with the resist structure in place, to remove the exposed insulator materials to form a plurality of apertures to the electrically conductive layer; and
forming electrically conductive materials within the plurality of apertures for forming the lithographically-defined conductive vias, each lithographically-defined conductive via having a width that is less than a trackwidth of the read sensor to be formed from the sensor stack structure and is located within boundaries defined by the trackwidth of the read sensor.
2. The method of claim 1 , wherein the width of each of the lithographically-defined conductive vias is less than or equal to ½ of the trackwidth of the read sensor.
3. The method of claim 1 , wherein the step of performing the lithographic process comprises the further step of performing a photolithography process.
4. The method of claim 1 , wherein the step of performing the lithographic process comprises the further step of performing an electron beam (e-beam) lithography process.
5. The method of claim 1 , wherein the lithographically-defined conductive vias are formed below the electrically conductive layer.
6. A method of making a current-perpendicular-to-plane (CPP) read sensor having a constrained current path, the method comprising the acts of:
forming a sensor stack structure;
performing a lithographic process to form a current-constraining structure adjacent an electrically conductive layer of the sensor stack structure, the current-constraining structure comprising a lithographically-defined conductive via surrounded by insulator materials, the lithographic process comprising the further acts of:
forming an insulator layer over the electrically conductive layer;
forming a resist structure over the insulator layer which exposes insulator materials of the insulator layer;
etching, with the resist structure in place, to remove the exposed insulator materials to form an aperture to the electrically conductive layer; and
forming electrically conductive materials within the aperture for forming the lithographically-defined conductive via, which has a width that is less than or equal to ½ of a trackwidth of the read sensor to be formed from the sensor stack structure and is located within boundaries defined by the trackwidth of the read sensor.
7. The method of claim 6 , further comprising:
wherein the act of performing the lithographic process comprises the further act of performing the lithographic process to form the current constraining structure with a plurality of lithographically-defined conductive vias surrounded by the insulator materials;
wherein the act of etching to remove the exposed insulator materials comprises forming a plurality of apertures to the electrically conductive layer; and
wherein the act of forming electrically conductive materials further comprises forming the electrically conductive materials with the plurality of apertures to thereby form the plurality of lithographically-defined conductive vias, each lithographically-defined conductive via located within the boundaries defined by the trackwidth of the read sensor.
8. The method of claim 6 , wherein the act of forming the current-constraining structure comprises forming the current-constraining structure where the lithographically-defined via is only a single lithographically-defined conductive via.
9. The method of claim 6 , wherein the step of performing the lithographic process comprises the further step of performing a photolithography process.
10. The method of claim 6 , wherein the step of performing the lithographic process comprises the further step of performing an electron beam (e-beam) lithography process.
11. The method of claim 6 , wherein the lithographically-defined conductive via is formed below the electrically conductive layer.