Wiring structure of a semiconductor device
View Patent ↗A mesh source wiring composed of first source wirings, second source wirings, and contacts for mesh source wiring is connected, through contacts for strap source wiring, with strap source wirings formed on a wiring layer nearer a substrate than wiring layers where the mesh source wiring is formed. The cell source wirings formed on a wiring layer nearer the substrate than the wiring layer where the strap source wirings are formed are connected with the strap source wirings through contacts for cell source wiring.
1. A semiconductor device having a substrate and a plurality of wiring layers including first, second, third, and fourth wiring layers, comprising:
a plurality of first source wirings formed in parallel with each other on the first wiring layer;
a plurality of second source wirings formed in a direction intersecting at a right angle with the first source wirings on the second wiring layer, the second wiring layer being located nearer the substrate than the first wiring layer;
a plurality of third source wirings formed on the third wiring layer, the third layer being located nearer the substrate than the second wiring layer;
a plurality of fourth source wirings formed on the fourth wiring layer, the fourth wiring layer being located nearer the substrate than the third wiring layer;
a first contact that connects one of the first source wirings and one of the second source wirings with each other at a part where the first source wiring and the second source wiring intersect with each other;
a second contact that connects one of the third source wirings and at least one of the first source wirings and the second source wirings with each other; and
a third contact that connects one of the third source wirings and one of the fourth source wirings with each other;
wherein the number of second contacts is less than the number of third contacts, and
a plurality of signal wiring layers are included between the second wiring layer and the third wiring layer, and a plurality of signal wiring layers are included between the third wiring layer and the fourth wiring layer.
2. The semiconductor device of claim 1 ,
wherein at least one of the third source wirings intersects with the second source wirings or is overlaid in parallel with corresponding one of the second source wirings.
3. The semiconductor device of claim 2 ,
wherein the third source wirings are overlaid in parallel with the second source wirings, respectively.
4. The semiconductor device of claim 3 ,
wherein the second contact is formed at at least one of parts where the first source wirings and the third source wirings intersect with each other and parts where the second source wirings and the third source wirings intersect with each other.
5. The semiconductor device of claim 2 ,
wherein the second contact is formed at at least one of parts where the first source wirings and the third source wirings intersect with each other and parts where the second source wirings and the third source wirings intersect with each other.
6. The semiconductor device of claim 1 ,
wherein the second contact is formed at at least one of parts where the first source wirings and the third source wirings intersect with each other and parts where the second source wirings and the third source wirings intersect with each other.
7. The semiconductor device of claim 1 ,
wherein the first wiring layer is provided the farthest from the substrate.
8. The semiconductor device of claim 1 ,
wherein respective wiring widths and respective wiring intervals of the first source wirings, the second source wirings, and the third source wirings are set so that an amount of voltage drop of source voltage in an circuit element to which source power is supplied becomes a predetermined value or smaller.
9. The semiconductor device of claim 1 ,
wherein signal wirings are formed in the first wiring layer, the second wiring layer, and the third wiring layer.
10. The semiconductor device of claim 1 ,
wherein the first source wirings, the second source wirings, and the third source wirings are overlaid with a circuit element on a plane projected to the substrate.
11. The semiconductor device of claim 1 ,
wherein the fourth source wirings intersect at a right angle with to the third source wirings.
12. The semiconductor device of claim 11 ,
wherein the third contact is formed at at least one of parts where the third source wirings and the fourth source wirings intersect with each other.
13. A semiconductor device having a substrate and a plurality of wiring layers including first, second, third, and fourth wiring layers, comprising:
a plurality of first source wirings formed in parallel with each other on the first wiring layer;
a plurality of second source wirings formed in a direction intersecting at a right angle with the first source wirings on the second wiring layer, the second wiring layer being located nearer the substrate than the first wiring layer;
a plurality of third source wirings formed on the third wiring layer, the third layer being located nearer the substrate than the second wiring layer;
a plurality of fourth source wirings formed on the fourth wiring layer, the fourth wiring layer being located nearer the substrate than the third wiring layer;
a first contact that connects one of the first source wirings and one of the second source wirings with each other at a part where the first source wiring and the second source wiring intersect with each other;
a second contact that connects one of the third source wirings and at least one of the first source wirings and the second source wirings with each other; and
a third contact that connects one of the third source wirings and one of the fourth source wirings with each other;
at least one standard cell, wherein said fourth source wiring layer is directly coupled to at least one standard cell; and
wherein the number of second contacts is less than the number of third contacts, and
a plurality of signal wiring layers are included between the second wiring layer and the third wiring layer, and a plurality of signal wiring layers are included between the third wiring layer and the fourth wiring layer.