Semiconductor memory device capable of compensating for leakage current

1. A semiconductor memory device, comprising:

a plurality of phase-change memory cells disposed at intersections of word lines and bit lines:

a plurality of dummy cells connected to at least one dummy bit line;

a leakage compensation circuit connected to the at least one dummy bit line that outputs a leakage compensation current to at least one of the bit lines; and

a read current supply circuit that outputs a read current necessary for a read operation to at least one of the bit lines in response to a first control signal.

2. The device of claim 1 , wherein each dummy cell includes a transistor of which a gate and a source are connected to a ground voltage, and a drain is connected to one terminal of a resistor made of phase-change material where another terminal of the resistor is connected to the at least one dummy bit line.

3. The device of claim 1 , further comprising a mode selection circuit that connects the at least one dummy bit line with the leakage compensation circuit in response to a third control signal.

4. The device of claim 3 , wherein the third control signal is determined based on a voltage level connected through a fuse circuit.

5. The device of claim 1 , wherein the first control signal contains read operation information.

6. The device of claim 1 , wherein the first control signal is a DC signal.

7. The device of claim 1 , further comprising a column selection circuit for connecting a selected bit line with the leakage compensation circuit and the read current supply circuit in response to a column selection signal.

8. The device of claim 7 , further comprising a dummy column selection circuit of which a gate is connected to a power source voltage, a source is connected to the at least one dummy bit line and a drain is connected to the leakage compensation circuit.

9. The device of claim 7 further comprising a clamping circuit for clamping a voltage of at least one of the bit lines at a predetermined level in a read operation in response to a second control signal.

10. The device of claim 9 , further comprising a dummy clamping circuit for clamping a voltage of the at least one dummy bit line at a predetermined level in a read operation in response to the second control signal.

11. A semiconductor memory device including a plurality of memory arrays, the device comprising:

a plurality of memory mats comprising each memory array; and

a plurality of memory blocks comprising each memory mat,

where the memory block comprises,

plurality of phase-change memory cells disposed at intersections of word lines and bit lines;

a plurality of dummy cell is connected to a first dummy bit line positioned in a first end of the memory block;

a leakage compensation circuit that is connected to the first dummy bit line that outputs a leakage compensation current to at least one of the bit lines; and

a read current supply circuit for outputting a read current necessary for a read operation to at least one of the bit lines in response to a first control signal.

12. The device of claim 11 further composing a second dummy bit line positioned in a second end of the memory block.

13. The device of claim 11 further comprising a mode selection circuit for connecting the first dummy bit line with the leakage compensation circuit in response to a third control signal.

14. The device of claim 11 wherein each memory cell includes a first transistor of which a gate is connected to at least one of the word lines, a source is connected to a ground voltage and a drain is connected to one terminal of a first resistor made of phase-change material where another terminal of the first resistor is connected to at least one of the bit lines, and

each dummy cell includes a second transistor of which a gate and a source are connected to the ground voltage, and a drain is connected to one terminal of a second resistor made of phase-change material where another terminal of the second resistor is connected to the first dummy bit line.

15. The device of claim 14 further comprising a column selection circuit for connecting a selected bit line with the leakage compensation circuit and the read current supply circuit in response to a column selection signal.

16. The device of claim 15 , further comprising a clamping circuit for clamping a voltage of at least one of the bit lines and the first dummy bit me at a predetermined level in a read operation in response to a second control signal.

17. A semiconductor memory device, comprising:

a plurality of phase-change memory cells disposed at intersections of word lines and bit lines:

a read current supply circuit for supplying a read current determined in a read operation to a sensing node connected to one of the bit lines;

a leakage compensation circuit for generating a leakage compensation current based on an amount of leakage current flowing through on-selected memory cells connected to the same one of the bit lines, and for applying the leakage compensation current to the sensing node; arid

a sense amplifier circuit for comparing a voltage of the sensing node, to which the leakage compensation current was applied, with a sensing reference voltage, and for performing a data read opera don for a selected memory cell.

18. The device of claim 17 wherein the leakage compensation on circuit senses leakage current flowing through dummy cells adjacent to the memory cells.

19. A read operation method in a phase-change memory device having a plurality of phase-change memory cells disposed at intersections of word lines and bit lines, the method comprising:

applying a read current to the bit line of a selected memory cell;

sensing leakage current for non-selected memory cells connected to the same bit line;

generating a leakage compensation current corresponding to an amount of the leakage current, and applying the leakage compensating current to a sensing node;

comparing a voltage of the sensing node, to which the leakage compensation current was applied, with a sensing reference voltage; and

reading out data stored in the selected memory cell.