Ferroelectric memory, multivalent data recording method and multivalent data reading method

1. A ferroelectric memory device, comprising:

a semiconductor body including a channel region of a first conductivity type;

a gate electrode formed on said semiconductor body in correspondence to said channel region in said semiconductor body via a ferroelectric film;

first and second diffusion regions of second conductivity type formed in said semiconductor body at respective lateral sides of said channel region,

said ferroelectric film comprising: a first ferroelectric region located in the vicinity of said first diffusion region; a second ferroelectric region located in the vicinity of said second diffusion region; and a third ferroelectric region located between said first and second regions,

said first, second and third regions carrying respective, mutually independent polarizations.

2. The ferroelectric memory device as claimed in claim 1 , further comprising:

a driver circuit applying respective drive voltages to said gate electrode, said first and second diffusion regions and said semiconductor body and inducing respective polarizations in said first through third regions of said ferroelectric film; and

a data discrimination circuit supplied multivalent data and controlling said driver circuit in response to a value of said multivalent data,

said driver circuit carrying out: a first writing step that induces identical polarization to all of said first through third regions; and a second writing step after said first writing step for causing reversal of said polarization in one of said first, second and third regions.

3. The ferroelectric memory device as claimed in claim 1 , wherein said driver circuits carries out any of the operations of: (1) applying a writing voltage of a first polarity to said gate electrode and grounding said first and second diffusion regions and said semiconductor body; (2) applying a writing voltage of a second polarity to said gate electrode and grounding said first and second diffusion regions and said semiconductor body; (3) applying, after said step (1), said writing voltage of said second polarity to said gate electrode, said first and second diffusion regions and grounding said semiconductor body; (4) applying, after said step (2), said writing voltage of said first polarity to said gate electrode, floating said first and second diffusion regions, and grounding said semiconductor body; (5) applying, after said step (1), said writing voltage of said second polarity to said gate electrode, said first diffusion region and said semiconductor body and grounding said second diffusion region; (6) applying, after said step (1), said writing voltage of said second polarity to said gate electrode, said second diffusion region and said semiconductor body and grounding said first diffusion region; (7) applying, after said step (2), said writing voltage of said first polarity to said gate electrode and said semiconductor body, grounding said first diffusion region, and floating said second diffusion region; and (8) applying, after said step (2), said writing voltage of said first polarity to said gate electrode and said semiconductor body, floating said first the diffusion region and grounding said second diffusion region.

4. The ferroelectric memory device as claimed in claim 1 , further comprising a reading circuit carrying out: a first reading step of detecting a first drain current by applying a read gate voltage to said gate electrode and applying a first read drain voltage to said first diffusion region; a second reading step of detecting a second drain current by applying a read gate voltage to said gate electrode and applying a second read drain voltage to said second diffusion region,

said ferroelectric memory device further comprising a data determination circuit determining a combination of polarizations induced respectively in said first, second and third regions from a combination of said first and second drain currents.

5. A semiconductor memory device, comprising:

a semiconductor body containing Si as a primary constituent element;

an insulation film formed on said semiconductor body in correspondence to a channel region in said semiconductor body;

a ferroelectric film formed on said insulation film;

a gate electrode formed on said ferroelectric film;

source and drain regions formed in said semiconductor body at respective lateral sides of said channel region,

wherein said insulation film comprises lamination of an amorphous film containing silicon oxide as a primary component and a polycrystal film containing HfO 2 as a primary component.

6. The ferroelectric memory device as claimed in claim 5 , wherein said amorphous film has a film thickness of 2-5 nm.

7. The ferroelectric memory device as claimed in claim 5 , wherein said polycrystal film comprises any of HfO 2 , HfSiOx, HfAlOx and HfSiON.

8. The ferroelectric memory device as claimed in claim 5 , wherein said ferroelectric film comprises a polycrystal film of any of Pb(Zr,Ti)O 3 , SrBi 2 Ta 2 O 9 , (Bi,La) 4 Ti 3 O 12 , (Bi,Nd) 4 Ti 3 O 12 , Bi 4 Ti 3 O 12 and Pb 5 Ge 3 O 11 .

9. The ferroelectric memory device as claimed in claim 8 , wherein said ferroelectric film is further doped with a trace element.

10. The ferroelectric memory device as claimed in claim 5 , wherein said gate electrode comprises a laminated film including a conductive oxide film at an interface to said ferroelectric film.

11. The ferroelectric memory device as claimed in claim 10 , wherein said conductive oxide film comprises any of IrO 2 , RuO 2 and SrRuO 3 .