Method for forming integrated circuit utilizing dual semiconductors
View Patent ↗A monolithically integrated electronic circuit using two different semiconductor layers which are separated by a dielectric layer. Transistors formed in the upper semiconductor layer are connected to transistors formed in the lower semiconductor layer via conventional wiring. Preferably, one layer of transistors is of one polarity, N-type or P-type, while the second layer of transistors is of the opposite polarity.
1. An electronic integrated circuit, comprising:
a first single-crystal semiconductor layer comprising silicon and having a first processing temperature, the first-single crystal semiconductor layer comprising at least one transistor formed therein;
a second single-crystal semiconductor layer comprising a germanium alloy and having a second processing temperature, the second-single crystal semiconductor layer overlapping the first single-crystal semiconductor layer and comprising at least one transistor formed therein;
a layer of substantially pure germanium having a third processing temperature, the layer of substantially pure germanium overlapping the first and second single-crystal semiconductor layers;
wherein the third processing temperature is lower than the second processing temperature;
wherein the second processing temperature is lower than the first processing temperature; and
wherein the first single-crystal semiconductor layer and the second single-crystal semiconductor layer are monolithically integrated.
2. The electronic integrated circuit of claim 1 wherein the layer of substantially pure germanium is grown from at least one germanium seed element, the germanium seed element grown epitaxially from said second single-crystal semiconductor layer.
3. The electronic integrated circuit of claim 1 wherein a majority of devices of one polarity are formed in said first single-crystal semiconductor layer, and a majority of devices of an opposite polarity are formed in said second single-crystal semiconductor layer.
4. An electronic integrated circuit, comprising:
a first semiconductor layer comprising a first semiconductor material, the first semiconductor layer having at least one transistor;
a layer of substantially pure germanium having at least one transistor; and
an insulating layer intermediate the first semiconductor layer and the layer of substantially pure germanium and at least partially separating the first semiconductor layer and the layer of substantially pure germanium;
wherein the layer of substantially pure germanium is integrated with the first semiconductor layer by growth from at least one germanium seed element, the at least one germanium seed element epitaxially grown from the first semiconductor layer at least partially through the insulating layer;
wherein said at least one transistor in said first semiconductor layer and said at least one transistor in said layer of substantially pure germanium are of opposite polarity.
5. The electronic integrated circuit of claim 4 wherein the at least one transistor in the layer of substantially pure germanium is a P-type transistor.
6. The electronic integrated circuit of claim 4 wherein said first semiconductor material comprises silicon and said at least one transistor in said first semiconductor layer is an N-type transistor.
7. The electronic integrated circuit of claim 6 wherein said at least one transistor in said layer of substantially pure germanium is a P-type transistor.
8. The electronic integrated circuit of claim 7 wherein said N-type transistor has a first speed and said P-type transistor has a second speed, and wherein the first speed and the second speed are substantially the same.
9. The electronic integrated circuit of claim 7 wherein said N-type transistor and said P-type transistor have substantially the same surface areas and speeds.
10. An electronic integrated circuit, comprising:
a first semiconductor layer comprising a first semiconductor material, the first semiconductor layer having at least one transistor;
a second semiconductor layer comprising a second semiconductor material, the second semiconductor layer having at least one transistor;
a first insulating layer intermediate said first and second semiconductor layers;
a layer of substantially pure germanium having at least one transistor; and
a second insulating layer intermediate the second semiconductor layer and the layer of substantially pure germanium;
wherein the second semiconductor layer is integrated with the first semiconductor layer by growth from at least one seed element of the second semiconductor material, the seed element epitaxially grown from the first semiconductor layer at least partially through the first insulating layer;
wherein said layer of substantially pure germanium is integrated with said second semiconductor layer by growth from at least one germanium seed element, said at least one germanium seed element epitaxially grown from said second semiconductor layer at least partially through said second insulating layer.
11. The electronic integrated circuit of claim 1 , wherein the at least one transistor of the first single-crystal semiconductor layer is connected to the at least one transistor of the second single-crystal semiconductor layer.
12. The electronic integrated circuit of claim 1 , wherein the layer of substantially pure germanium comprises at least one transistor formed therein.
13. The electronic integrated circuit of claim 12 , wherein the at least one transistor of the layer of substantially pure germanium is connected to the at least one transistor of the second single-crystal semiconductor layer.
14. The electronic integrated circuit of claim 12 , wherein the at least one transistor of the layer of substantially pure germanium is connected to the at least one transistor of the first single-crystal semiconductor layer.
15. The electronic integrated circuit of claim 7 , wherein the at least one transistor of the first semiconductor layer is connected to the at least one transistor of the layer of substantially pure germanium.
16. The electronic integrated circuit of claim 10 , wherein the at least one transistor of the first semiconductor layer is connected to the at least one transistor of the second semiconductor layer.
17. The electronic integrated circuit of claim 10 , wherein the at least one transistor of the second semiconductor layer is connected to the at least one transistor of the layer of substantially pure germanium.
18. The electronic integrated circuit of claim 10 , wherein the at least one transistor of the first semiconductor layer is connected to the at least one transistor of the layer of substantially pure germanium.