Constant-weight-code-based addressing of nanoscale and mixed microscale/nanoscale arrays
View Patent ↗Various embodiments of the present invention include methods for determining nanowire addressing schemes and include microscale/nanoscale electronic devices that incorporate the nanowire addressing schemes for reliably addressing nanowire-junctions within nanowire crossbars. The addressing schemes allow for change in the resistance state, or other physical or electronic state, of a selected nanowire-crossbar junction without changing the resistance state, or other physical or electronic state, of the remaining nanowire-crossbar junctions, and without destruction of either the selected nanowire-crossbar junction or the remaining, non-selected nanowire-crossbar junctions. Additional embodiments of the present invention include nanoscale memory arrays and other nanoscale electronic devices that incorporate the nanowire-addressing-scheme embodiments of the present invention. Certain of the embodiments of the present invention employ constant-weight codes, a well-known class of error-control-encoding codes, as addressed-nanowire selection voltages applied to microscale output signal lines of microscale/nanoscale encoder-demultiplexers that are selectively interconnected with a set of nanowires.
1. An encoder-demultiplexer comprising:
k input signal lines;
an encoder that generates an n-bit-constant-weight-code-codeword internal address for each different external address received on the k input signal lines;
n output signal lines on which an n-bit-constant-weight-code-codeword internal address is output by the encoder; and
a number of encoder-demultiplexer-addressed signal lines interconnected with the n output signal lines, the encoder-demultiplexer-addressed signal lines each associated with an n-bit-constant-weight-code-codeword internal address.
2. The encoder-demultiplexer of claim 1 wherein the n output signal lines are selectively interconnected with the encoder-demultiplexer-addressed signal lines so that, when the encoder outputs a particular n-bit-constant-weight-code-codeword internal address to the n output signal lines, a signal is input to an encoder-demultiplexer-addressed signal line associated with the n-bit-constant-weight-code-codeword internal address that is distinguishable from signals input to all encoder-demultiplexer-addressed signal lines not associated with the n-bit-constant-weight-code-codeword internal address.
3. The encoder-demultiplexer of claim 1 wherein the signal input to the encoder-demultiplexer-addressed signal line associated with the n-bit-constant-weight-code-codeword internal address that is distinguishable from signals input to all encoder-demultiplexer-addressed signal lines not associated with the n-bit-constant-weight-code-codeword internal address is a voltage signal of greater magnitude than voltage signals output to all encoder-demultiplexer-addressed signal lines not associated with the n-bit-constant-weight-code-codeword internal address.
4. The encoder-demultiplexer of claim 1 wherein the signal input to the addressed signal line associated with the n-bit-constant-weight-code-codeword internal address that is distinguishable from signals input to all addressed signal lines not associated with the n-bit-constant-weight-code-codeword internal address is a voltage signal of smaller magnitude than voltage signals output to all addressed signal lines not associated with the n-bit-constant-weight-code-codeword internal address.
5. The encoder-demultiplexer of claim 1 wherein the signal input to the addressed signal line associated with the n-bit-constant-weight-code-codeword internal address that is distinguishable from signals input to all encoder-demultiplexer-addressed signal lines not associated with the n-bit-constant-weight-code-codeword internal address is a current signal of greater magnitude than voltage signals output to all encoder-demultiplexer-addressed signal lines not associated with the n-bit-constant-weight-code-codeword internal address.
6. The encoder-demultiplexer of claim 1 wherein the signal input to the encoder-demultiplexer-addressed signal line associated with the n-bit-constant-weight-code-codeword internal address that is distinguishable from signals input to all encoder-demultiplexer-addressed signal lines not associated with the n-bit-constant-weight-code-codeword internal address is a current signal of smaller magnitude than voltage signals output to all encoder-demultiplexer-addressed signal lines not associated with the n-bit-constant-weight-code-codeword internal address.
7. The encoder-demultiplexer of claim 1 wherein the k input signal lines and the n output signal lines are microscale signal lines, the encoder is implemented in microscale or submicroscale logic, and the number of encoder-demultiplexer-addressed signal lines are nanowires.
8. The encoder-demultiplexer of claim 1 that, along with a second encoder-demultiplexer, addresses nanowire-crossbar junctions in a nanowire crossbar.
9. The encoder-demultiplexer of claim 1 that addresses linearly ordered nanoscale components of a nanoscale or mixed-scale device.
10. The encoder-demultiplexer of claim 1 that, along with a additional encoder-demultiplexers, addresses nanoscale components of a nanoscale or mixed-scale device arranged in 3 or more logical dimensions.
11. The encoder-demultiplexer of claim 1 wherein the constant-weight code has a minimal q d ratio for the size M of the constant-weight code, where the q d ratio is a ratio of the maximum distance between different codewords and the minimum distance between codewords of the constant-weight code, wherein k equal to ceiling(M), and wherein the number of encoder-demultiplexer-addressed signal lines is less than or equal to M.
12. A nanoscale memory array comprising:
a nanowire crossbar with a first set of i parallel nanowires and a second set of j parallel nanowires, the nanowires of the first and second sets of nanowires not parallel to one another, and therefore forming a grid with points of closest contact between each nanowire of the first set of parallel nanowires and each nanowire of the second set of parallel nanowires forming nanowire junctions;
a first encoder-demultiplexer that controls voltages on the first set of parallel nanowires by outputting voltage patterns equivalent to codewords of a constant-weight code with size M≧i; and
a second encoder-demultiplexer that controls voltages on the second set of parallel nanowires by outputting voltage patterns equivalent to codewords of a constant-weight code with size M≧j.
13. The nanoscale memory array of claim 12 wherein the nanowire junctions operate as hysteretic resistors with well defined WRITE-access thresholds and destruction thresholds.
14. The nanoscale memory array of claim 12 wherein each of the first and second encoder-demultiplexers outputs voltage patterns equivalent to codewords of a constant-weight code onto microscale output signal lines selectively interconnected to the set of parallel nanowires controlled by the first and second encoder-demultiplexers so that, for each output codeword, a selected nanowire with an internal nanowire address equal to the codeword is placed in a voltage state closest to the source voltage of the encoder-demultiplexer, and all non-selected nanowires are placed in voltage states further from the source voltage than the selected nanowire.
15. The nanoscale memory array of claim 14 wherein a nanowire junction between nanowires currently selected by the two encoder-demultiplexers is selected, and all other nanowire junctions are not selected.
16. The nanoscale memory array of claim 15 wherein the constant-weight codes provide sufficient voltage separations between a selected nanowire and non-selected nanowires to ensure that a voltage of magnitude greater than the WRITE-access threshold but less than the destruction thereshold is dropped across the selected nanowire junction, while voltages less than the WRITE-access threshold are dropped across the non-selected nanowire junctions.
17. The nanoscale memory array of claim 16 wherein the constant-weight codes provide q v ratios, where q v is the ratio between a voltage of greatest magnitude output to a non-selected nanowire to the magnitude of a voltage output to the selected nanowire, sufficient to provide a specified voltage margin between the magnitude of the voltage dropped across the selected nanowire junction and the magnitude of the voltage dropped across a non-selected nanowire junction closest to the magnitude of the voltage dropped across the selected nanowire junction.
18. The nanoscale memory array of claim 17 wherein the constant-weight codes have q d ratios, where the q d ratio is the ratio of the maximum distance between different codewords and the minimum distance between codewords, sufficient to provide the q v ratios.
19. A method for addressing a number of signal lines, the method comprising:
determining a number of signal lines i that need to be addressed;
determining a signal margin needed between a signal output to a selected, addressed signal line and any signal output to a non-selected, addressed signal line; and
implementing a constant-weight-code-based encoder-demultiplexer to address the number of signal lines.
20. The method of claim 19 wherein the constant-weight code has a minimal q d ratio for the size M of the constant-weight code, where the q d ratio is a ratio of the maximum distance between different codewords and the minimum distance between codewords of the constant-weight code, and i≦M.
21. The method of claim 19 wherein the constant-weight code is one of the constant-weight codes:
(8,70,2,4);
(9,84,2,3);
(11,66,4,5);
(15,70,6,6); and
(20,64,8,8).
22. The method of claim 19 wherein the signals are voltages.
23. The method of claim 19 the encoder-demultiplexer comprises:
k input signal lines;
an encoder that generates an n-bit-constant-weight-code-codeword internal address for each different external address received on the k input signal lines; and
n output signal lines, on which an n-bit-constant-weight-code-codeword internal address is output by the encoder, interconnected with the i signal lines, the i signal lines each associated with an n-bit-constant-weight-code-codeword internal address.