Schedule prediction for data link layer packets

1. A port operable for a PCI Express link, comprising:

a scheduler operable to determine a next management packet transmission time;

a windower operable to determine a transmission window based upon the next management packet transmission time;

an evaluative forward-looker to determine an optimum scheduling for a data transfer link management packet based on the number of received TLPs, actual TLP sizes, and receive buffer status,

wherein the evaluate forward-looker analyzes an upcoming TLP stream to locate an existing gap between TLPs at a position in the TLP stream which corresponds to a range of possible transmission times for the data transfer link management packet; and

an inserter operable to examine a data packet stream to determine whether a gap therein occurs during the transmission window, and if such said gap does occur to control insertion of a management packet thereinto.

2. The port of claim 1 , wherein the scheduler is operable to determine a transmission time on the basis of at least one of: a flow control timer, a receive acknowledge timer, and an available transmission credit monitor.

3. The port of claim 1 , wherein the windower is operable to determine the window on the basis of at least one of: a desired link responsiveness, a management packet transmission urgency and received data packet size.

4. The port of claim 1 , wherein the inserter comprises a packet generator operable to generate a management packet for insertion into the data packet stream.

5. The port of claim 1 , operable for multiple lane links.

6. The port of claim 1 , wherein the inserter is operable if no such gap does occur to control creation of a gap between two data packets and insertion of the management packet thereinto.

7. The port of claim 1 , wherein the inserter is operable if no such gap does occur to not send a management packet.

8. The port of claim 1 , wherein the inserter is operable to identify a gap split between consecutive cycles and to rotate a management packet to fit into such a split gap.

9. An integrated circuit design for use in creation of an integrated circuit operable as the port of claim 1 .

10. The integrated circuit design of claim 9 , expressed using a hardware definition language.

11. The port of claim 1 , wherein the port is implemented as an integrated circuit.

12. A port operable for a PCI Express link, comprising:

scheduler means for determining a next management packet transmission time;

windower means for determining a transmission window based upon the next management packet transmission time;

an evaluative forward-looking means to determine an optimum scheduling for a data transfer link management packet based on the number of received TLPs, actual TLP sizes, and receive buffer status,

wherein the evaluative forward-looking means analyzes an upcoming TLP stream to locate an existing gap between TLPs at a position in the TLP stream which corresponds to a range of possible transmission times for the data transfer link management packet; and

inserter means for examining a data packet stream to determine whether a gap therein occurs during the transmission window, and

if such said gap does occur for controlling insertion of a management packet thereinto.

13. A method for controlling insertion of link management packets into a data packet stream for a PCI Express port, the method comprising:

determining a next management packet transmission time;

determining a transmission window based upon the determined next management packet transmission time;

examining a data packet stream for gaps therein during the determined transmission window;

using evaluative forward-looking to determine an optimum scheduling for a data transfer link management packet based on the number of received TLPs, actual TLP sizes, and receive buffer status,

wherein using evaluative forward-looking comprises analyzing an upcoming TLP stream to locate an existing gap between TLPs at a position in the TLP stream which corresponds to a range of possible transmission times for the data transfer link management packet; and

inserting a management packet into such a gap, if said gap is identified.

14. The method of claim 13 , wherein the determining a transmission time is performed on the basis of at least one of a flow control timer, a receive acknowledge timer, and an available transmission credit monitor.

15. The method of claim 13 , wherein the determining a transmission window is performed on the basis of at least one of a desired link responsiveness, a management packet transmission urgency and received data packet size.

16. The method of claim 13 , wherein inserting comprises generating a management packet for insertion into the data packet stream.

17. The method of claim 13 , for multiple lane links.

18. The method of claim 13 , wherein the inserting comprises creation of a gap between two data packets if no such gap is identified and inserting of the management packet thereinto.

19. The method of claim 13 , wherein the insertion is not performed if no such gap is identified.

20. The method of claim 13 , wherein the examining comprises identifying a gap split between consecutive cycles, and wherein the inserting comprises rotating a management packet to fit into such a split gap.

21. An integrated circuit design for use in creation of an integrated circuit operable to carry out the method of claim 13 .

22. The integrated circuit design of claim 21 , expressed using a hardware definition language.

23. A computer readable medium storing instructions that, when executed by a computer, cause the computer to perform a method for controlling insertion of link management packets into a data packet stream for a PCI Express port, the method comprising:

determining a next management packet transmission time;

determining a transmission window based upon the determined next management packet transmission time;

examining a data packet stream for gaps therein during the determined transmission window;

using evaluative forward-looking to determine an optimum scheduling for a data transfer link management packet based on the number of received TLPs, actual TLP sizes, and receive buffer status,

wherein using evaluative forward-looking comprises analyzing an upcoming TLP stream to locate an existing gap between TLPs at a position in the TLP stream which corresponds to a range of possible transmission times for the data transfer link management packet; and

inserting a management packet into such a gap, if said gap is identified.

24. An integrated circuit for controlling insertion of link management packets into a data packet stream for a PCI Express port, the integrated circuit comprising:

scheduling circuitry for determining a next management packet transmission time;

window circuitry for determining a transmission window based upon the determined next management packet transmission time;

examination circuitry for examining a data packet stream to identify a gap therein during the determined transmission window;

evaluative forward-looking circuitry for determining an optimum scheduling for a data transfer link management packet based on the number of received TLPs, actual TLP sizes, and receive buffer status,

wherein the evaluate forward-looking circuitry analyzes an upcoming TLP stream to locate an existing gap between TLPs at a position in the TLP stream which corresponds to a range of possible transmission times for the data transfer link management packet; and

insertion circuitry for inserting a management packet into such said gap, if said gap is identified.