Randomized self-checking test system
View Patent ↗Methods and apparatus are provided for verifying and validating operation of a design under test (DUT). Input data sequences having information used to check expected outputs are provided to a DUT. The input data sequences include checking headers and data. The checking headers and data are randomized using encryption to verify and validate operation of the DUT on a variety of bit sequences. Different keys are used to allow further scrambling.
1. A method for performing verification testing, the method comprising:
providing an input data sequence including a checking header, wherein the checking header includes information characterizing a relationship between the input data sequence and an output data sequence;
encrypting the input data sequence including the checking header to obtain an encrypted input data sequence including an encrypted checking header;
sending the encrypted input data sequence to a design under test, wherein the design under test performs processing on the encrypted input data sequence and provides an encrypted output data sequence;
decrypting the encrypted output data sequence;
determining a relationship between the output data sequence and the input data sequence by using the checking header to determine that the design under test is operating properly.
2. The method of claim 1 , wherein the design under test is a resource virtualization switch.
3. The method of claim 1 , wherein the design under test is virtualization logic associated with a resource virtualization switch.
4. The method of claim 1 , wherein the design under test is virtualization application specific integrated circuit (ASIC) associated with a resource virtualization switch.
5. The method of claim 1 , wherein the checking header identifies content of the input data sequence.
6. The method of claim 1 , wherein the checking header identifies a path the input data sequence is supposed to follow.
7. The method of claim 1 , wherein the checking header identifies a software descriptor.
8. The method of claim 1 , wherein the checking header identifies a packet flow.
9. The method of claim 1 , wherein the checking header identifies a memory address where the output data sequence should be stored.
10. The method of claim 1 , wherein the checking header allows comparison of fields included in the output data sequence to expected fields.
11. The method of claim 1 , wherein encryption and decryption is disabled to debug a test data sequence.
12. The method of claim 1 , wherein encryption and decryption are enabled to debug the design under test.
13. The method of claim 1 , wherein the checking header identifies a software descriptor.
14. The method of claim 1 , wherein the encrypted data sequence includes an encrypted transaction identifier and an encrypted sequence identifier.
15. The method of claim 14 , wherein the TCP/IP headers remain unencrypted.
16. The method of claim 14 , further comprising adding an entry to a transaction table prior to encrypted the data sequence.
17. The method of claim 14 , wherein the data sequence is a part of a packet.
18. The method of claim 14 , wherein the checking header includes a pointer to a transaction table.
19. A computer readable storage medium having computer code embedded therein, the computer readable storage medium comprising:
computer code for providing an input data sequence including a checking header, wherein the checking header includes information characterizing a relationship between the input data sequence and an output data sequence;
computer code for encrypting the input data sequence including the checking header to obtain an encrypted input data sequence including an encrypted checking header;
computer code for sending the encrypted input data sequence to a design under test, wherein the design under test performs processing on the encrypted input data sequence and provides an encrypted output data sequence;
computer code for decrypting the encrypted output data sequence;
computer code for determining a relationship between the output data sequence and the input data sequence by using the checking header to determine that the design under test is operating properly.
20. The computer readable storage medium of claim 19 , wherein the design under test is a resource virtualization switch.
21. The computer readable storage medium of claim 19 , wherein the design under test is virtualization logic associated with a resource virtualization switch.
22. The computer readable storage medium of claim 19 , wherein the design under test is virtualization application specific integrated circuit (ASIC) associated with a resource virtualization switch.
23. The computer readable storage medium of claim 19 , wherein the checking header identifies content of the input data sequence.
24. The computer readable storage medium of claim 19 , wherein the checking header identifies a path the input data sequence is supposed to follow.
25. The computer readable storage medium of claim 19 , wherein the checking header includes a pointer to a transaction table.
26. A system for performing verification testing, the system comprising:
means for providing an input data sequence including a checking header, wherein the checking header includes information characterizing a relationship between the input data sequence and an output data sequence;
means for encrypting the input data sequence including the checking header to obtain an encrypted input data sequence including an encrypted checking header;
means for sending the encrypted input data sequence to a design under test, wherein the design under test performs processing on the encrypted input data sequence and provides an encrypted output data sequence;
means for decrypting the encrypted output data sequence;
means for determining a relationship between the output data sequence and the input data sequence by using the checking header to determine that the design under test is operating properly.
27. The system of claim 26 , wherein the design under test is a resource virtualization switch.
28. The system of claim 26 , wherein the design under test is virtualization logic associated with a resource virtualization switch.
29. The system of claim 26 , wherein the design under test is virtualization application specific integrated circuit (ASIC) associated with a resource virtualization switch.
30. The system of claim 26 , wherein the checking header identifies content of the input data sequence.
31. The system of claim 26 , wherein the checking header identifies a path the input data sequence is supposed to follow.
32. The system of claim 26 , wherein the checking header identifies a software descriptor.
33. The system of claim 26 , wherein the checking header identifies a packet flow.
34. The system of claim 26 , wherein the checking header identifies a memory address where the output data sequence should be stored.