Multithreaded processor having a source processor core to subsequently delay continued processing of demap operation until responses are received from each of remaining processor cores

1. A processor comprising:

a plurality of processor cores, wherein each of the plurality of processor cores comprises at least one translation lookaside buffer (TLB); and

an interconnect to which the plurality of processor cores are coupled;

wherein a first processor core of the plurality of processor cores is configured to broadcast a demap command on the interconnect responsive to executing a demap operation in the first processor core, and wherein the demap command identifies one or more translations to be invalidated in each TLB in each of the plurality of processor cores, and wherein remaining processor cores of the plurality of processor cores are configured to invalidate the one or more translations in the respective TLBs and to transmit a response to the first processor core, and wherein the first processor core is configured to delay continued processing of the demap operation, including delaying invalidation of the one or more translations in the TLB in the first processor core, until the responses are received from each of the remaining processor cores.

2. The processor as recited in claim 1 wherein each of the plurality of processor cores is multithreaded.

3. The processor as recited in claim 2 wherein at least some strands in a given processor core share the TLB in that processor core, and wherein the demap operation is issued on only one of the sharing strands.

4. The processor as recited in claim 1 wherein the at least one TLB in each processor core comprises an instruction TLB and a data TLB in each processor core, and wherein invalidating the one or more translations comprises invalidating the one or more translations in one or both of the instruction TLB and the data TLB.

5. The processor as recited in claim 1 wherein each of the plurality of processor cores is programmable with a number of expected responses, and wherein the first processor core is configured to use the number of expected responses and a count of received responses to determine that all of the responses have been received from the remaining processor cores.

6. The processor as recited in claim 1 wherein the remaining processor cores are configured to process the demap command as if a locally executed demap operation occurred.

7. A processor comprising:

a plurality of processor cores, wherein each processor core of the plurality of processor cores comprises a plurality of strands, wherein each strand comprises hardware to support a different thread of a plurality of concurrently activateable threads in the processor core, and wherein each processor core further comprises at least one translation lookaside buffer (TLB); and

an interconnect to which the plurality of processor cores are coupled;

wherein a first processor core of the plurality of processor cores is configured to broadcast a demap command on the interconnect responsive to executing a demap operation in the first processor core, and wherein the demap command identifies one or more translations to be invalidated in each TLB in each of the plurality of processor cores, and wherein remaining processor cores of the plurality of processor cores are configured to invalidate the one or more translations in the respective TLBs and to transmit a response to the first processor core, and wherein the first processor core is configured to delay continued processing of the demap operation, including delaying invalidation of the one or more translations in the TLB in the first processor core, until the responses are received from each of the remaining processor cores.

8. The processor as recited in claim 7 wherein each of the plurality of processor cores is programmable with a number of expected responses, and wherein the first processor core is configured to use the number of expected responses and a count of received responses to determine that all of the responses have been received from the remaining processor cores.

9. The processor as recited in claim 7 wherein at least two strands in the first processor core share the TLB in the first processor core, and wherein the demap operation is issued on only one of the sharing strands.

10. The processor as recited in claim 7 wherein the at least one TLB in each processor core comprises an instruction TLB and a data TLB in each processor core, and wherein invalidating the one or more translations comprises invalidating the one or more translations in one or both of the instruction TLB and the data TLB.

11. The processor as recited in claim 7 wherein the remaining processor cores are configured to process the demap command as if a locally executed demap operation occurred.

12. A method for a system that includes a plurality of processor cores, wherein each of the plurality of processor cores comprises at least one translation lookaside buffer (TLB), and an interconnect to which the plurality of processor cores are coupled, the method comprising:

a first processor core of the plurality of processor cores executing a demap operation;

responsive to executing the demap operation, the first processor core of the plurality of processor cores broadcasting a demap command on the interconnect, wherein the demap command identifies one or more translations to be invalidated in each TLB in each of the plurality of processor cores;

remaining processor cores of the plurality of processor cores invalidating the one or more translations in the respective TLBs;

each remaining processor core transmitting a response to the first processor core; and

the first processor core delaying continued processing of the demap operation, including delaying invalidation of the one or more translations in the TLB in the first processor core, until the responses are received from each of the remaining processor cores.

13. The method as recited in claim 12 wherein each of the plurality of processor cores is multithreaded.

14. The method as recited in claim 13 wherein at least some strands in a given processor core share the TLB in that processor core, the method further comprising the demap operation issuing on only one of the sharing strands.

15. The method as recited in claim 12 wherein the at least one TLB in each processor core comprises an instruction TLB and a data TLB in each processor core, and wherein invalidating the one or more translations comprises invalidating the one or more translations in one or both of the instruction TLB and the data TLB.

16. The method as recited in claim 12 further comprising:

programming each of the plurality of processor cores with a number of expected responses; and

the first processor core using the number of expected responses and a count of received responses to determine that all of the responses have been received from the remaining processor cores.

17. The method as recited in claim 12 further comprising the remaining processor cores processing the demap command as if a locally executed demap operation occurred.