Manufacturing process for a transistor made of thin layers
View Patent ↗A process for fabricating a transistor that includes a gate located in the immediate proximity of a dielectric includes a step of etching a layer of gate material. The gate etching step includes plasma etching of the gate layer over the major portion of its thickness so as to laterally define the gate and chemical etching of a residual portion of the gate layer so as to define the gate as far as the dielectric.
1. A process for fabricating a transistor comprising a gate located in immediate proximity to a dielectric layer comprising silicon oxide having a thickness of less than about 3 nm, the process comprising:
etching a layer of gate material, the etching step including,
plasma etching the layer of gate material over a major portion of thickness so as to laterally define the gate and leaving a residual portion of the layer of gate material; and
implanting a chemical species into the residual portion and chemically etching the residual portion so as to define the gate on the dielectric layer.
2. The process according to claim 1 , wherein the residual portion has a thickness of about 10 nm or less.
3. The process according to claim 1 , wherein the dielectric layer has a thickness of less than about 2 nm.
4. The process according to claim 3 , wherein the dielectric layer has a thickness of greater than about 0.6 nm.
5. The process according to claim 1 , wherein the layer of gate material comprises a first sublayer covered by a second sublayer, the first sublayer and the second sublayer comprising different materials.
6. The process according to claim 5 , wherein the first sublayer comprises a material less sensitive to the plasma etching than the second sublayer.
7. The process according to claim 5 , wherein the second sublayer comprises a multilayer.
8. The process according to claim 1 , wherein the layer of gate material comprises a uniform layer.
9. The process according to claim 1 , wherein the plasma etching further comprises an oxygen-based end-of-etching step.
10. The process according to claim 1 , wherein the chemical etching comprises wet chemical etching.
11. The process according to claim 1 , wherein the residual portion comprises a material whose work function is configured to provide a predefined threshold voltage of the transistor.
12. A process for fabricating a transistor comprising a gate located in immediate proximity to a dielectric layer, the process comprising:
etching a uniform layer of gate material, the etching step including plasma etching of the uniform layer of gate material over a major portion of thickness so as to laterally define the gate;
implanting a chemical species in a residual portion of the uniform layer; and
chemically etching the residual portion so as to define the gate on the dielectric layer.
13. A process for fabricating a transistor comprising a gate located in proximity to a dielectric layer of high permittivity material having a thickness of about 7 nm or less, the process comprising:
etching a layer of gate material, etching step including,
plasma etching the layer of gate material over the major portion of thickness so as to laterally define the gate and leaving a residual portion of layer of gate material; and
implanting a chemical species into the residual portion and chemically etching the residual portion so as to define the gate on the dielectric layer.
14. The process according to claim 13 , wherein the residual portion has a thickness of about 10 nm or less.
15. The process according to claim 13 , wherein the dielectric layer has a thickness of less than about 2 nm.
16. The process according to claim 15 , wherein the dielectric layer has a thickness of greater than about 0.6 nm.
17. The process according to claim 13 , wherein the layer of gate material comprises a first sublayer covered by a second sublayer, the first sublayer and the second sublayer comprising different materials.
18. The process according to claim 17 , wherein the first sublayer comprises a material less sensitive to the plasma etching than the second sublayer.
19. The process according to claim 17 , wherein the second sublayer comprises a multilayer.
20. The process according to claim 13 , wherein the layer of gate material comprises a uniform layer.
21. The process according to claim 13 , wherein the plasma etching further comprises an oxygen-based end-of-etching step.
22. The process according to claim 13 , wherein the chemical etching comprises wet chemical etching.
23. The process according to claim 13 , wherein the residual portion comprises a material whose work function is configured to provide a predefined threshold voltage of the transistor.