Semiconductor devices having amorphous silicon-carbon dielectric and conducting layers
View Patent ↗A method for fabricating a semiconductor device having a plurality of layers, depositing a first layer comprising a medium-k dielectric barrier layer on one of the plurality of layers, depositing a second layer comprising a low-k dielectric layer on the first layer, and depositing a third layer comprising a medium-k dielectric barrier on the second layer.
1. A semiconductor device having a plurality of layers, including a low-k dielectric layer and medium-k dielectric layers, wherein the low-k dielectric layer is positioned between the medium-k dielectric layers, and the low-k dielectric layer and the medium-k dielectric layers comprise a stabilized synergetic carbon.
2. The device of claim 1 wherein the low-k dielectric layer has a dielectric constant not exceeding 3.0.
3. The device of claim 1 wherein the medium-k dielectric layers comprising stabilized synergetic carbon have a dielectric constant in the range from about 3 to about 5.9.
4. The device of claim 1 wherein the medium-k dielectric layers comprising stabilized synergetic carbon have a dielectric constant in the range of 4 to 5.
5. The device of claim 1 wherein the medium-k dielectric layers are resistant to water or vapor.
6. The device of claim 1 wherein the medium-k dielectric layers prevent atomic diffusion or ion electro-diffusion penetration into the semiconductor.
7. The device of claim 1 wherein the medium-k dielectric layers mechanically reinforce the low-k dielectric layer.
8. The device of claim 1 wherein said low-k dielectric layer comprises strain-controlling materials.
9. The device of claim 8 wherein the low-k dielectric layer has a dielectric constant not exceeding 3.0.