IP Library Granted Patent US 7,335,952
Granted Patent B2
US 7,335,952 · App. 11/224,013 · Granted Feb 26, 2008

Semiconductor device and manufacturing method therefor

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Quick Facts
Patent No.
US 7,335,952
App. No.
11/224,013
Granted
Feb 26, 2008
Kind
B2
Abstract

To provide a semiconductor device that permits free setting of characteristics of individual semiconductor elements which are mixedly mounted and have different characteristics, and is free of steps between formed semiconductor elements, in a manufacturing method for the semiconductor device, an n-type silicon layer is deposited on a p-type silicon substrate by epitaxial growth, and then an SOI layer is deposited thereon through the intermediary of a BOX layer. A junction transistor using a part of the n-type silicon layer as a channel region and a MOS transistor using the SOI layer are produced.

Claims (43)

1. A semiconductor device comprising:

a first silicon substrate of a first conductive type including a first region and a second region;

a second silicon substrate of a second conductive type different from the first conductive type, the second silicon substrate being formed on the first silicon substrate;

a buried oxide layer formed on an upper surface of the second silicon substrate;

a first transistor formed on the buried oxide layer directly above the second region of the first silicon substrate; and

a second transistor formed in the second silicon substrate on the first region of the first silicon substrate.

2. The semiconductor device according to claim 1 , wherein the second transistor is a junction transistor.

3. The semiconductor device according to claim 1 , wherein:

the junction transistor includes a part of the second silicon substrate as a channel region;

the first silicon substrate is formed of p-type silicon; and

the second silicon substrate is formed of n-type silicon.

4. The semiconductor device according to claim 1 , wherein the first transistor is a MOS transistor including a drain region formed of an n-type silicon substrate and a channel region formed of a p-type silicon substrate.

5. The semiconductor device according to claim 4 , wherein the first silicon substrate is formed of n-type silicon, and the second silicon substrate formed of p-type silicon.

6. The semiconductor device according to claim 1 , further comprising a separating layer formed in a groove shape around the second transistor, the separating layer surrounding and electrically isolating the second transistor.

7. The semiconductor device according to claim 1 , further comprising a third silicon substrate formed on the buried oxide layer directly above the second region of the first silicon substrate, wherein the first transistor is a MOS transistor including a source layer and a drain layer between which the third silicon substrate is disposed.

8. The semiconductor device according to claim 1 , wherein the second transistor is a junction transistor including (i) a source layer, a drain layer and a gate layer formed respectively in the second silicon substrate, and (ii) buried polysilicon layers formed respectively on the source, drain and gate layers.

9. The semiconductor device according to claim 1 , further comprising a third silicon substrate formed on the buried oxide layer directly above the second region of the first silicon substrate, wherein:

the first transistor is a MOS transistor including a source layer and a drain layer between which the third silicon substrate is disposed; and

the second transistor is a junction transistor including (i) a source layer, a drain layer and a gate layer formed respectively in the second silicon substrate, and (ii) buried polysilicon layers formed respectively on the source, drain and gate layers.

10. A semiconductor device comprising:

a first silicon substrate of a first conductive type including a first region and a second region;

a second silicon substrate of a second conductive type different from the first conductive type, the second silicon substrate being formed on the first silicon substrate;

a buried oxide layer formed on an upper surface of the second silicon substrate;

a junction transistor formed in the second silicon substrate on the first region of the first silicon substrate;

a MOS transistor formed on the buried oxide layer directly above the second region of the first silicon substrate; and

a separation layer formed between the junction transistor and the MOS transistor.

11. The semiconductor device according to claim 10 , wherein the junction transistor includes (i) a source layer, a drain layer and a gate layer formed respectively in the second silicon substrate, and (ii) buried polysilicon layers formed respectively on the source, drain and gate layers.

12. The semiconductor device according to claim 11 , wherein:

the junction transistor further includes a part of the second silicon substrate, which is disposed between the source layer and the drain layer of the junction transistor, as a channel region;

the first silicon substrate is formed of p-type silicon; and

the second silicon substrate is formed of n-type silicon.

13. The semiconductor device according to claim 11 , wherein the junction transistor further includes salicide layers formed respectively on a top surface of each of the buried polysilicon layers.

14. The semiconductor device according to claim 11 , wherein each of the buried polysilicon layers penetrates through the buried oxide layer.

15. The semiconductor device according to claim 10 , further comprising a third silicon substrate formed on the buried oxide layer directly above the second region of the first silicon substrate, wherein the MOS transistor includes a source layer and a drain layer between which the third silicon substrate is disposed.

16. The semiconductor device according to claim 15 , wherein:

the drain region of the MOS transistor is formed of an n-type silicon substrate; and

the third silicon substrate between the source layer and the drain layer of the MOS transistor is a channel region of the MOS transistor and is formed of a p-type silicon substrate.

17. The semiconductor device according to claim 15 , wherein the third silicon substrate between the source layer and the drain layer of the MOS transistor is a channel region of the MOS transistor and is formed of an n-type silicon substrate.

18. The semiconductor device according to claim 15 , wherein the MOS transistor further includes salicide layers formed respectively on the source layer and the drain layer.

19. The semiconductor device according to claim 10 , further comprising a third silicon substrate formed on the buried oxide layer directly above the second region of the first silicon substrate, wherein:

the junction transistor includes (i) a source layer, a drain layer and a gate layer formed respectively in the second silicon substrate, and (ii) buried polysilicon layers formed respectively on the source, drain and gate layers; and

the MOS transistor includes a source layer and a drain layer between which the third silicon substrate is disposed.

20. The semiconductor device according to claim 10 , wherein the separating layer is formed in a groove shape around the junction transistor, and surrounds and electrically isolates the junction transistor.

Assignments (1)
CHANGE OF NAME Recorded Dec 24, 2008
From: OKI ELECTRIC INDUSTRY CO., LTD.
To: OKI SEMICONDUCTOR CO., LTD.
Reel/Frame 022052/0797 →