Thin film transistor array panel and liquid crystal display
View Patent ↗A thin film transistor array panel is provided, which includes an insulating substrate, a gate line formed on the insulating substrate, a gate insulating layer covering the gate line, a data line formed on the gate insulating layer, a lower passivation layer covering the data line, an upper passivation layer formed on the lower passivation layer and made of organic insulating material, and a pixel electrode formed on the upper passivation layer. The thicknesses of the gate insulating layer, the lower passivation layer, and the pixel electrode are respectively represented as d G , d P , and d I , the refraction indexes of the gate insulating layer, the passivation layer, and the pixel electrode are respectively represented as n G , n P , and n I , and condition equations are satisfied according to: 4( d G n G +d P n P )=, which is an even multiple of the wavelength; and 4d I n I =, which is an even multiple of the wavelength.
1. A thin film transistor array panel, comprising:
an insulating substrate;
a gate line formed on the insulating substrate;
a gate insulating layer covering the gate line;
a data line formed on the gate insulating layer;
a lower passivation layer covering the data line;
an upper passivation layer formed on the lower passivation layer and comprising an organic insulating material; and
a pixel electrode formed on the upper passivation layer,
wherein the gate insulating layer, the lower passivation layer, and the pixel electrode satisfy the following condition equations:
4( d G n G +d P n P )=which is an even multiple of a wavelength of light; and
4 d I n I =which is an even multiple of the wavelength, and,
wherein the thicknesses of the gate insulating layer, the lower passivation layer, and the pixel electrode are represented as d G , d P , and d I , respectively, and the refraction index of the gate insulating layer, the passivation layer, and the pixel electrode are represented as n G , n p , and n I , respectively.
2. The thin film transistor array panel of claim 1 , wherein the lower passivation layer comprises a silicon nitride.
3. The thin film transistor array panel of claim 2 , wherein the refraction index of the silicon nitride is between approximately 1.8-1.9.
4. The thin film transistor array panel of claim 1 , wherein the refraction index of the pixel electrode is between approximately 1.8-1.9.
5. The thin film transistor array panel of claim 1 , wherein the refraction index of the upper passivation layer is between approximately 1.4-1.6.
6. A liquid crystal display, comprising:
a first substrate;
a gate insulating layer formed on the first substrate;
a lower passivation layer formed on the gate insulating layer;
an upper passivation layer formed on the lower passivation layer and comprising an organic insulating material;
a pixel electrode formed on the upper passivation layer;
a second substrate facing the first substrate; and
a liquid crystal layer formed between the first substrate and the second substrate,
wherein the gate insulating layer, the lower passivation layer, and the pixel electrode satisfy the following condition equations:
4( d G n G +d p n p )=which is an even multiple of a wavelength of light, and
4 d 1 n 1 =which is an even multiple of the wavelength, and
wherein the thicknesses of the gate insulating layer, the lower passivation layer, and the pixel electrode are represented as d G , d p , and d 1 , respectively, and the refraction index of the gate insulating layer, the passivation layer, and the pixel electrode are represented as n G , n p , and n 1 , respectively.