Multivibrator protected against current or voltage spikes

1. A multivibrator protected against current or voltage spikes, comprising:

a first data transfer port that receives, as input, multivibrator input data;

a first, master, latch cell connected on the output side of the first transfer port;

a second, slave, latch cell; and

a second data transfer port placed between the first and second latch cells;

wherein each latch cell comprises a set of redundant data storage nodes and wherein the transfer ports each comprise means for writing data separately into each storage node.

2. The multivibrator according to claim 1 , wherein each latch cell comprises four storage nodes and wherein the transfer ports each comprise four separate write circuits for writing the data into the four storage nodes, respectively.

3. The multivibrator according to claim 2 , wherein each write circuit comprises a first n type MOS transistor, the gate of which receives data coming from a data storage node of the first latch cell and the drain of which is connected to the source of a second n type MOS transistor, the gate of which receives a clock signal and the drain of which is used to write the data into a storage node of the second latch cell.

4. The multivibrator according to claim 1 , further comprising an input circuit suitable for generating redundant data for the first latch cell.

5. The multivibrator according to claim 4 , wherein the input circuit comprises an inverter circuit for inverting input data, the output of which is intended to be written into data storage nodes.

6. The multivibrator according to claim 1 , further comprising an output circuit protected against current or voltage spikes and placed on the output side of the second data storage cell.

7. The multivibrator according to claim 6 , wherein the output circuit comprises two stages, one for transferring data in the high state and the other for transferring data in the low state.

8. The multivibrator according to claim 7 , wherein the stage for transferring data in the low state comprises a first p type MOS transistor, the gate of which receives data in the low state and the source of which is connected to a DC supply, and a second p type MOS transistor, the source of which is connected to the drain of the first MOS transistor, the gate of which receives data in the low state and the drain of which delivers data as output from the multivibrator.

9. The multivibrator according to claim 8 , wherein the stage for transferring data in the high state comprises a first n type MOS transistor, the gate of which receives data in the high state and the drain of which is connected to the drain of the second p type MOS transistor and delivers data as output from the multivibrator, and a second n type MOS transistor, the drain of which is connected to the source of the first n type MOS transistor, the gate of which receives data in the high state and the source of which is connected to earth/ground.

10. A multivibrator, comprising:

a master latch cell; and

a slave latch cell coupled to the master latch cell;

wherein, each latch cell comprises:

a pair of true data storage nodes;

a pair of false data storage nodes;

wherein the true data storage nodes are separated by a distance that is greater than a diameter of an ionized particle capable of generating a current or voltage spike in the cell, and

wherein the false storage nodes are separated by a distance that is greater than a diameter of an ionized particle capable of generating a current or voltage spike in the cell.

11. The multivibrator of claim 10 wherein the distance of separation is greater than one micron.

12. A multivibrator, comprising:

a master latch cell; and

a slave latch cell coupled to the master latch cell;

wherein, each latch cell comprises:

a pair of true data storage nodes at the drain terminals of first and second transistors;

a pair of false data storage nodes at the drain terminals of third and fourth transistors;

wherein the first and second transistors for the true data storage nodes are implanted in different wells of a first conductivity type, and

wherein the third and fourth transistors for the false data storage nodes are implanted in different wells of the first conductivity type.

13. The multivibrator of claim 12 ,

wherein the true data storage nodes are separated by a distance that is greater than a diameter of an ionized particle capable of generating a current or voltage spike in the cell, and

wherein the false data storage nodes are separated by a distance that is greater than a diameter of an ionized particle capable of generating a current or voltage spike in the cell.

14. The multivibrator of claim 12 wherein the true data storage nodes are separated from each other, as well as the false data storage nodes are separated from each other, by a distance of at least one micron.

15. The multivibrator of claim 12 wherein the first and third transistors are implanted in a first well of the first conductivity type and the second and fourth transistors are implanted in a second well of the first conductivity type, the cell further including at least one additional transistor implanted in a well of a second conductivity type, wherein the well of the second conductivity type is positioned between the first and second wells of the first conductivity type.

16. An integrated circuit multivibrator comprising:

a semiconductor substrate including a region for a master and slave latches of the multivibrator;

a plurality of transistors formed in a center area of the region;

first and second transistors associated with a pair of true data storage nodes for each of the master and slave latches;

third and fourth transistors associated with a pair of false data storage nodes for each of the master and slave latches;

wherein the first and second transistors for each latch are formed in the region on opposite sides of the center area and wherein the third and fourth transistors for each latch are formed in the region on opposite sides of the center area.

17. The circuit of claim 16 wherein first and second transistors are separated by a distance and the third and fourth transistors are separated by distance each greater than a diameter of an ionized particle capable of generating a current or voltage spike in the cell.

18. The circuit of claim 16 wherein first and second transistors are separated by a distance and the third and fourth transistors are separated by distance each of at least one micron.

19. The circuit of claim 16 wherein the first and third transistors are formed in a first well of a first conductivity type and the second and fourth transistors are formed in a second well also of the first conductivity type, and wherein the center area of the region comprises a well of a second conductivity type in which the plurality of transistors are implanted.

20. The circuit of claim 19 wherein the first conductivity type is n-type and the second conductivity type is p-type.