System and method for detecting and recovering from errors in an instruction stream of an electronic data processing system
View Patent ↗A system and method are provided for detecting and recovering from errors in an Instruction Cache RAM and/or Operand Cache RAM of an electronic data processing system. In some cases, errors in the Instruction Cache RAM and/or Operand Cache RAM are detected and recovered from without any required interaction of an operating system of the data processing system. Thus, and in many cases, errors in the Instruction Cache RAM and/or Operand Cache RAM can be handled seamlessly and efficiently, without requiring a specialized operating system routine, or in some cases, a maintenance technician, to help diagnose and/or fix the error.
1. A pipelined instruction processor having a number of pipelined stages, comprising:
an instruction queue for storing one or more instructions;
an instruction selector for selecting a selected instruction from the instruction queue and for providing the selected instruction to the pipelined stages of the instruction processor for execution;
a parity error detector for identifying which, if any, of the one or more instructions in the instruction queue, including the selected instruction, have a parity error, the parity error detector identifying which, if any, of the one or more instructions in the instruction queue have a parity error prior to the instruction selector selecting the selected instruction for execution by the pipelined stages of the instruction processor, the parity error detector setting a parity error bit for each of those queued instructions that have been identified as having a parity error, wherein the parity error bit, when set, indicates that the corresponding queued instruction has a parity error; and
an error handler for issuing a parity error abort message if the instruction selected by the instruction selector has a parity error.
2. The pipelined instruction processor of claim 1 , wherein the error handler is a parity error handler.
3. The pipelined instruction processor of claim 2 , wherein the parity error handler halts execution of the selected instruction.
4. The pipelined instruction processor of claim 3 , further comprising a first level cache for providing instructions to the instruction queue, and a second level cache for providing instructions to the first level cache, and wherein the parity error handler causes the selected instruction to be reloaded from the second level cache into the first level cache, and to the pipelined stages for re-execution.
5. The pipelined instruction processor of claim 4 , wherein the selected instruction is initially read from a first portion of the first level cache, and wherein the parity error handler causes the selected instruction to be reloaded from the second level cache and into a second portion of the first level cache.
6. The pipelined instruction processor of claim 5 , wherein the first portion of the first level cache is marked but still available for use.
7. The pipelined instruction processor of claim 6 , wherein if a subsequent instruction is read from a marked portion of the first level cache and it is determined to have a parity error by the parity error handler, the marked portion of the first level cache is degraded and no longer used.
8. The pipelined instruction processor of claim 7 , further comprising a maintenance processor, wherein the maintenance processor reports how many and/or which portions of the first level cache have been degraded and no longer used.
9. The pipelined instruction processor of claim 4 , wherein the parity error detector checks those instructions that are read from the first level cache as they are provided to the instruction queue, the parity error detector identifies those instructions that have a parity error by setting a corresponding parity error bit that is stored along with the instructions in the instruction queue.
10. The pipelined instruction processor of claim 9 , wherein the number of pipelined stages includes a first pipeline stage, and wherein the first pipeline stage includes a storage location for storing the parity error bit provided by the instruction queue.
11. The pipelined instruction processor of claim 10 , wherein the parity error handler reads the parity error bit from the storage location in the first pipeline stage, and if the parity error bit is set, issues the parity error abort message.
12. A method for operating a pipelined instruction processor having a number of pipelined stages, the method comprising:
queuing one or more instructions;
identifying which, if any, of the one or more queued instructions have a parity error;
setting a parity error bit for those queued instructions that have been identified as having a parity error, wherein the parity error bit, when set, indicates that the corresponding queued instruction has a parity error;
selecting a selected one of the one or more instructions for execution;
after the selected instructions has been selected for execution, determining if the selected instruction has a parity error by determining if the selected instruction has a parity error bit that has been set by the setting step;
halting execution of the selected instruction if the determining step determines that the selected instruction has a parity error; and
executing the selected instruction if the selected instruction does not have a parity error.
13. The method of claim 12 further comprising the step of issuing a parity error abort message if the selected instruction is determined to have a parity error.
14. The method of claim 13 further comprising the steps of:
storing the one or more queued instructions in an instruction queue;
providing one or more of the queued instructions to the instruction queue from a first level cache;
providing one or more of the queued instructions to the first level cache from a second level cache; and
reloading the selected instruction from the second level cache to the first level cache if the selected instruction has a parity error.
15. The method of claim 14 wherein the selected instruction is initially read from a first portion of the first level cache, and wherein the selected instruction is reloaded from the second level cache into a second portion of the first level cache.
16. The method of claim 15 further comprising the step of marking the first portion of the first level cache.
17. The method of claim 16 further comprising the step of degrading a marked portion of the first level cache if a subsequent instruction is read from the marked portion of the first level cache and is determined to have a parity error.
18. The method of claim 17 further comprising the step of reporting how many and/or which portions of the first level cache have been degraded.
19. The method of claim 14 wherein the identifying step identifies those instructions that have a parity error as they are read from the first level cache and provided to the instruction queue.
20. The method of claim 19 wherein the parity error bit is stored along with those instructions that have a parity error in the instruction queue.
21. The method of claim 19 wherein the number of pipelined stages includes a first pipeline stage, and wherein the first pipeline stage includes a storage location for storing the parity error bit provided by the instruction queue.
22. The method of claim 21 further comprising the steps of checking the parity error bit in the storage location of the first pipeline stage, and issuing the parity error abort message if the selected instruction has a parity error.
23. A method for operating a pipelined instruction processor having a number of pipelined stages, the method comprising:
detecting a parity error in one or more instructions before the pipelined instruction processor actually calls the one or more instructions for execution by the pipelined stages of the instruction processor; and
deferring interruption of the pipelined instruction processor until the pipelined instruction processor actually calls for execution of an instruction that has a detected parity error.
24. A method for operating a cache memory that has a number of memory locations, the method comprising:
reading a data word from a selected memory location of the cache memory;
checking the data word for a parity error, and if a parity error is present:
checking to see if the selected memory location was previously marked a predetermined number of times as having previously provide a data word with a parity error, and if so, degrading the selected memory location to prevent the selected memory location from further use, and if not, marking the selected memory location; and
writing another copy of the data word to the cache memory.
25. The method of claim 24 wherein the another copy of the data word is written to a different memory location in the cache memory than the selected memory location.
26. A method for operating a cache memory that has a number of memory locations, the method comprising:
reading a data word from a selected memory location of the cache memory;
checking the data word for a parity error, and if a parity error is present:
checking to see if the selected memory location was previously marked as having previously provide a data word with a parity error, and if so, degrading the selected memory location to prevent the selected memory location from further use, and if not, marking the selected memory location;
writing another copy of the data word to the cache memory;
counting the number of degrades for the cache memory; and
issuing an alert if the number of degrades for the cache memory exceeds a predetermined threshold.
27. The method of claim 24 wherein the cache memory is part of an operand cache memory.
28. The method of claim 27 wherein the cache memory is part of an instruction cache memory.