IP Library Granted Patent US 7,362,330
Granted Patent B2
US 7,362,330 · App. 11/226,964 · Granted Apr 22, 2008

Adaptive span computation when ray casting

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Quick Facts
Patent No.
US 7,362,330
App. No.
11/226,964
Granted
Apr 22, 2008
Kind
B2
Abstract

A processor uses start point fractional values during view screen segment computations that start a view screen segment's computations a particular distance away from a down point. This prevents an excessive sampling density during image generation without wasting processor resources. The processor identifies a start point fractional value for each view screen segment based upon each view screen segment's identifier, and computes a view screen segment start point for each view screen segment using the start point fractional value. View screen segment start points are “tiered” and are a particular distance away from the down point. This stops the view screen segments from converging to a point of severe over sampling while, at the same time, providing a pseudo-uniform sampling density.

Claims (32)

1. A computer-implemented method comprising:

identifying a down point location;

determining one or more start point fractional values based upon the down point location;

selecting one of the start point fractional values for a view screen segment, wherein the selecting further comprises:

identifying a view screen segment identifier that corresponds to the view screen segment;

determining a last bit value of the view screen segment identifier;

selecting a fifty percent start point fractional value in response to determining that the last bit value is one;

in response to determining that the last bit value is zero, determining a second to last bit value of the view screen segment identifier;

selecting a twenty five percent start point fractional value in response to determining that the second to last bit value is one;

in response to determining that the second to last bit value is zero, determining a third to last bit value of the view screen segment identifier; and

selecting a twelve and one-half percent start point fractional value in response to determining that the third to last bit value is one;

computing a view screen segment start point using the selected start point fractional value;

generating image values corresponding to the view screen segment starting at the view screen segment start point; and

displaying the image values on a view screen.

2. The method of claim 1 wherein the computing further comprises:

identifying the distance between the down point location and a view screen edge that corresponds to the view screen segment;

multiplying the selected start point fractional value with the identified distance, resulting in a start point fractional distance; and

adding the start point fractional distance to the down point location, resulting in the view screen segment start point.

3. The method of claim 1 wherein the determining further comprises:

identifying the start point fractional values that are located within the view screen.

4. The method of claim 1 further comprising:

selecting a view screen intersection point based upon the view screen segment start point;

calculating a height map intersection point based upon the selected view screen intersection point;

retrieving height map data corresponding to the calculated height map intersection point; and

wherein the generation of the image values includes the retrieved height map data.

5. The method of claim 1 further comprising:

identifying a pixel resolution corresponding to a plurality of pixels included in the view screen;

determining a view screen segment density for a plurality of view screen segments based upon the pixel resolution, the view screen segment included in the plurality of view screen segments; and

wherein the view screen segment density ensures that one or more of the plurality of view screen segments corresponds to generating image values for each of the plurality of pixels.

6. The method of claim 1 further comprising:

wherein the method is performed using a broadband processor architecture, the broadband processor architecture including a plurality of heterogeneous processors, a common memory, and a common bus; and

wherein the plurality of heterogeneous processors use different instruction sets and share the common memory and the common bus.

Assignments (1)
CHANGE OF NAME Recorded Dec 20, 2021
From: FACEBOOK, INC.
To: META PLATFORMS, INC.
Reel/Frame 058553/0802 →