Method for fabricating semiconductor device
View Patent ↗A method for fabricating a semiconductor device including on a single semiconductor substrate, a first MOS transistor having a first gate insulating film of a predetermined thickness, and second and third MOS transistors sharing a second gate insulating film smaller in thickness than the first gate insulating film, the third MOS transistor being lower in threshold voltage than the second MOS transistor, the method includes the steps of: adjusting the threshold voltages of the first and third MOS transistors by first ion-implantation; and adjusting the threshold voltage of the second MOS transistor by second ion-implantation, the second ion-implantation being performed under implantation conditions different from those of the first ion-implantation.
1. A method for fabricating a semiconductor device comprising on a single semiconductor substrate, a first MOS transistor having a first gate insulating film of a predetermined thickness, and second and third MOS transistors sharing a second gate insulating film smaller in thickness than the first gate insulating film, the first, second and third MOS transistors being of the same conductivity type, the third MOS transistor being lower in threshold voltage than the second MOS transistor, comprising:
adjusting the threshold voltages of the first and third MOS transistors by first ion-implantation; and
adjusting the threshold voltage of the second MOS transistor by second ion-implantation, the second ion-implantation being performed under implantation conditions different from those of the first ion-implantation.
2. A method for fabricating a semiconductor device, comprising:
adjusting the threshold voltages of first and third MOS transistors while forming first and third MOS transistor formation regions in a semiconductor substrate by first ion-implantation;
forming a first gate insulating film having a predetermined thickness on the entire surface of the substrate;
adjusting the threshold voltage of a second MOS transistor while forming a second MOS transistor formation region in the substrate by second ion-implantation, the second ion-implantation being performed under different implantation conditions from those of the first ion-implantation;
exposing the substrate by removing a portion of the first gate insulating film above the second and third MOS transistors formation regions; and
forming a second gate insulating film on the exposed portion of the substrate so that the second gate insulating film is smaller in thickness than the first gate insulating film,
wherein the first, second and third MOS transistors are of the same conductivity type.
3. The method according to claim 1 , wherein the threshold voltage of the first MOS transistor is 0.5 V to 0.8 V, and the threshold voltage of the third MOS transistor is 0.05 V to 0.2 V.
4. The method according to claim 2 , wherein the threshold voltage of the first MOS transistor is 0.5 V to 0.8 V, and the threshold voltage of the third MOS transistor is 0.05 V to 0.2 V.
5. The method according to claim 1 , wherein the third MOS transistor is greater in gate length than the second MOS transistor.
6. The method according to claim 2 , wherein the third MOS transistor is greater in gate length than the second MOS transistor.
7. The method according to claim 1 , wherein the thickness of the first gate insulating film after the formation of the second gate insulating film is 10 nm to 16 nm, and the thickness of the second gate insulating film is 3 nm to 6 nm.
8. The method according to claim 2 , wherein the thickness of the first gate insulating film after the formation of the second gate insulating film is 10 nm to 16 nm, and the thickness of the second gate insulating film is 3 nm to 6 nm.