Memory addressing
Addressing memory includes receiving a first operand to a memory addressing operator, receiving a second operand to the memory addressing operator, performing sign extension on the first operand to provide a sign-extended operand, shifting the sign-extended operand to provide a shifted, sign-extended operand, and adding the shifted, sign-extended operand to the second operand. The second operand has a different bit length than the first operand.
1. A method of addressing an array having an array entry size in memory, comprising:
selecting a memory addressing operator according to a known array entry size, the memory addressing operator being selected from a plurality of memory addressing operators wherein each of the plurality of memory addressing operators corresponds to a different array entry size;
receiving a first operand to a memory addressing operator;
receiving a second operand to the memory addressing operator; the second operand having a different bit length than the first operand;
performing sign extension on the first operand, including by replicating a sign bit of the first operand, to provide a sign-extended operand;
shifting the sign-extended operand to provide a shifted, sign-extended operand; and
adding the shifted, sign-extended operand to the second operand.
2. A method as recited in claim 1 , wherein the second operand has a greater bit length than the first operand.
3. A method as recited in claim 1 , wherein the memory addressing operator is an instruction.
4. A method as recited in claim 1 , wherein the memory addressing operator is an addressing mode.
5. A method as recited in claim 1 , wherein the first operand represents an array entry index.
6. A method as recited in claim 1 , wherein the second operand represents a base address of an array.
7. A method as recited in claim 1 , wherein the first operand is a 32-bit operand and the second operand is a 64-bit operand.
8. A method as recited in claim 1 , wherein the first operand is a 16-bit operand and the second operand is a 32-bit operand.
9. A method as recited in claim 1 , wherein the memory is addressed by a 32-bit Java program in a 64-bit Java Virtual Machine environment.
10. A method as recited in claim 1 , wherein the memory addressing operator is selected from a plurality of memory addressing operators.
11. A method as recited in claim 1 , wherein adding the shifted, sign-extended operand to the second operand provides an entry address of an array entry.
12. A processor configured to address memory, comprising:
a first register configured to receive a first operand to a memory addressing operator; and
a second register configured to receive a second operand to the memory addressing operator; the second operand having a different number of bits than the first operand;
wherein the processor is configured to:
select a memory addressing operator according to a known array entry size, the memory addressing operator being selected from a plurality of memory addressing operators wherein each of the plurality of memory addressing operators corresponds to a different array entry size;
perform sign extension on the first operand, including by replicating a sign bit of the first operand, to provide a sign-extended operand;
shift the sign-extended operand to provide a shifted, sign-extended operand; and
add the shifted, sign-extended operand to the second operand.
13. A processor as recited in claim 12 , wherein the memory addressing operator is an instruction.
14. A processor as recited in claim 12 , wherein the memory addressing operator is an addressing mode.
15. A processor as recited in claim 12 , wherein the first operand represents an array entry index.
16. A processor as recited in claim 12 , wherein the second operand represents a base address of an array.
17. A processor as recited in claim 12 , wherein the first operand is a 32-bit operand and the second operand is a 64-bit operand.
18. A processor as recited in claim 12 , wherein the memory is addressed by a 32-bit Java program in a 64-bit Java Virtual Machine environment.
19. A processor as recited in claim 12 , wherein the memory addressing operator is selected from a plurality of memory addressing operators.
20. A processor as recited in claim 12 , wherein adding the shifted, sign-extended operand to the second operand provides an entry address of an array entry.