Ordering operation
Executing an ordering operation is disclosed. A store operation associated with storing a value into a portion of a memory is initiated. An ordering operation to ensure that the store operation, but not necessarily all store operations, are completed is executed.
1. A method of executing operations, including:
executing a memory allocation operation, including:
allocating a first memory space; and
initiating a store operation associated with storing an initialization value into a portion of a memory that is at a distance beyond the first allocated memory space;
executing an ordering operation to ensure that the store operation, but not necessarily all store operations, is completed at least prior to next memory allocation operation; and
executing the next memory allocation operation, including:
allocating a second memory space, the second memory space including at least a part of the portion of the memory that stores the initialization value.
2. A method as recited in claim 1 , wherein the allocated first memory space is associated with a memory object.
3. A method as recited in claim 1 , wherein the store operation is a different type of store operation from one or more other store operations not ensured to be ordered by the ordering operation.
4. A method as recited in claim 1 , wherein the store operation is associated with a cache invalidation of the portions of the memory cached in one or more processor caches.
5. A method as recited in claim 1 , wherein the store operation is not responsive to a fencing operation that fences non-initial-value-stores.
6. A method as recited in claim 1 , wherein the store operation includes storing the initial value to a cache without incurring a cache miss even if the portion of the memory is not cached.
7. A method as recited in claim 1 , wherein memory size of the portion of the memory is preconfigured or dynamically configured.
8. A method as recited in claim 1 , wherein the portion of the memory includes unallocated memory.
9. A method as recited in claim 1 , wherein the ordering operation includes a memory access operation and a fencing operation responsive to the memory access operation.
10. A method as recited in claim 9 , wherein the fencing operation is not responsive to the store of one or more initial values.
11. A method as recited in claim 9 , wherein the store operation completes only if the memory access instruction will not produce a cache miss.
12. A method as recited in claim 1 , wherein the ordering operation includes performing a load or a store operation to the portion of the memory.
13. A method as recited in claim 1 , wherein the ordering operation includes an address range specific fencing operation.
14. A method as recited in claim 13 , wherein the address range specific fencing operation causes only prior stores or loads associated with a specific memory address range to become visible before any future stores or loads become visible.
15. A method as recited in claim 1 , wherein at least a portion of the memory is heap memory.
16. A method as recited in claim 1 , wherein the method is implemented on one of the following: a processor, a program process, a thread, a processor instruction, a virtual machine, an interpreter, and a compiler.
17. A method as recited in claim 1 , further comprising executing a second ordering operation to ensure that all store operations are completed.
18. A method as recited in claim 1 , wherein the ordering operation includes a fencing operation responsive to all stores of initial values but not responsive to other types of stores or loads.
19. A method as recited in claim 1 , wherein executing the next memory allocation operation further includes initiating a second store operation associated with storing the initialization value into a second portion of the memory that is beyond the second allocated memory space.
20. A system for executing operations, including:
a memory; and
a processor coupled to the memory, configured to:
execute a memory allocation operation, including to:
allocate a first memory space; and
initiate a store operation associated with storing an initialization value into a portion of the memory that is at a distance beyond the first allocated memory space;
execute an ordering operation to ensure that the store operation, but not necessarily all store operations, is completed at least prior to next memory allocation operation; and
execute the next memory allocation operation including to:
allocate a second memory space, the second memory space including at least a part of the portion of the memory that stores the initialization value.
21. A system as recited in claim 20 , wherein the allocated memory space is associated with a memory object.
22. A system as recited in claim 20 , wherein the store operation is a different type of store operation from one or more other store operations not ensured to be ordered by the ordering operation.
23. A system as recited in claim 20 , wherein the processor initiates the store operation associated with storing the value into the portion of the memory including by executing an initial value store processor instruction.
24. A system as recited in claim 23 , wherein the initial value store processor instruction includes one or more of the following operands: an initial value operand, a memory location operand associated with the location to store the initial value, and a size operand associated with the amount of memory used to contain the initial value.
25. A system as recited in claim 20 , wherein the processor executes the ordering operation including by executing one of the following fencing instructions: a fencing instruction not responsive to the store of one or more initial values, an address range specific fencing instruction, and a fencing instruction responsive to all stores of initial values but not responsive to other types of stores or loads.
26. A system as recited in claim 20 , wherein the store operation is associated with a cache invalidation of the portions of the memory cached in caches coupled to other processors.
27. A system as recited in claim 20 , wherein the store operation includes storing one or more initial values to a cache without incurring a cache miss even if the portions of the memory is not cached.
28. A system as recited in claim 20 , wherein the ordering operation includes a memory access operation and a fencing operation responsive to the memory access operation.
29. A system as recited in claim 20 , wherein the ordering operation includes an address range specific fencing operation.
30. A system as recited in claim 20 , wherein to execute the next memory allocation operation further includes to initiate a second store operation associated with storing the initialization value into a second portion of the memory that is beyond the second allocated memory space.
31. A computer program product for executing operations, the computer program product being embodied in a computer readable storage medium and comprising computer instructions for:
executing a memory allocation operation, including:
allocating a first memory space; and
initiating a store operation associated with storing an initialization value into a portion of a memory that is at a distance beyond the first allocated memory space;
executing an ordering operation to ensure that the store operation, but not necessarily all store operations, is completed at least prior to next memory allocation operation; and
executing the next memory allocation operation, including:
allocating a second memory space, the second memory space including at least a part of the portion of the memory that stores the initialization value.