Cooperative preemption
Preempting the execution of a thread is disclosed. Preempting includes receiving an indication that a preemption of the thread is desired and context switching the thread out at a thread safe point in the event that a thread safe point is reached.
1. A method of preempting the execution of a thread, including:
receiving at a processor a first indication that a preemption of a first thread is desired in order to execute a second thread;
in response to receiving the first indication, waiting for the first thread to reach a thread safe point, the thread safe point being a point in code at which if the first thread were to stop at the thread safe point, an operation that a third thread may want to perform on the first thread can be performed, wherein the first thread, the second thread and the third thread are different threads;
in the event that the first thread reaches a thread safe point, context switching the first thread out at the thread safe point and context switching the second thread in;
in the event that the first thread has not reached a thread safe point and it is detected that a second indication has been received, in response to the detection, preemptively context switching the first thread out and context switching the second thread in; and
in the case of a single processor system, in the event that a fourth thread requests that all other threads be at a safe point, and each of the other threads has already entered a thread safe point, begin executing the fourth thread immediately.
2. A method as recited in claim 1 , wherein the second indication includes a timer interrupt.
3. A method as recited in claim 1 , wherein the second indication includes the expiry of a quantum.
4. A method as recited in claim 1 , wherein the second indication includes a request to interrupt the first thread.
5. A method as recited in claim 1 , wherein an operating system receives the first indication.
6. A method as recited in claim 1 , wherein the first indication includes an event.
7. A method as recited in claim 1 , wherein the first indication includes an event, wherein the event includes a thread of higher priority becoming ready to run.
8. A method as recited in claim 1 , wherein the first indication includes a timer interrupt.
9. A method as recited in claim 1 , wherein the first indication includes the expiry of a quantum.
10. A method as recited in claim 1 , wherein the first indication includes a request to preempt the first thread.
11. A method as recited in claim 1 , wherein the first indication includes an interrupt sent by another processor.
12. A method as recited in claim 1 , further including calling a thread exception.
13. A method as recited in claim 1 , wherein context switching includes setting a flag to indicate that a context switch at a thread safe point is required.
14. A method as recited in claim 1 , further including the first thread checking a flag for a third indication that a context switch at a thread safe point is required.
15. A method as recited in claim 1 , wherein context switching includes arming a thread safe point interrupt.
16. A method as recited in claim 1 , further including the first thread executing a safe point instruction that triggers an armed safe point interrupt.
17. A method as recited in claim 1 , further including calling a thread exception to indicate that a safe point interrupt has been triggered.
18. A method as recited in claim 1 , wherein the first thread receives a third indication that a safe point is reached via a thread exception.
19. A method as recited in claim 1 , wherein context switching the first thread out includes the first thread calling a system call while at a safe point.
20. A method as recited in claim 1 , wherein context switching the first thread out includes the first thread calling a system call while at a safe point if a third indication that a context switch at a safe point is required is received.
21. A method as recited in claim 1 , wherein at least one of the first thread, the second thread, and the third thread is running on a virtual machine.
22. A method as recited in claim 1 , further including performing garbage collection.
23. A method as recited in claim 1 , further including performing a debugging break point.
24. A method as recited in claim 1 , wherein lock ownership within a thread safe point is avoided.
25. A method as recited in claim 1 , further including sending a third indication that a preemption of a plurality of threads is desired.
26. A method as recited in claim 1 , wherein context switching includes context switching a plurality of threads.
27. A method as recited in claim 1 , further including sending a third indication that each of a plurality of threads needs to be at a thread safe point, wherein sending the indication includes setting a flag.
28. A method as recited in claim 1 , further including sending a third indication that each of a plurality of threads needs to be at a thread safe point, wherein sending the indication includes acquiring a lock.
29. A method as recited in claim 1 , further including sending a third indication that each of a plurality of threads needs to be at a thread safe point, wherein sending the indication includes setting a flag per thread.
30. A method as recited in claim 1 , further including sending a third indication that each of a plurality of threads needs to be at a thread safe point, wherein sending the indication includes acquiring a lock per thread.
31. A method as recited in claim 1 , further including sending a third indication that a global safe point is desired.
32. A method as recited in claim 31 , wherein the first indication includes an event, wherein the event includes a thread of higher priority becoming ready to run.
33. A method as recited in claim 32 , wherein context switching the first thread out includes the first thread calling a system call while at a safe point.
34. A method as recited in claim 33 , wherein sending the third indication includes acquiring a lock.
35. A method as recited in claim 31 , further including the first thread checking a flag for a fourth indication that a context switch at a thread safe point is required.
36. A method as recited in claim 31 , further including the first thread executing a safe point instruction that triggers an armed safe point interrupt.
37. A system for preempting the execution of a thread, including:
a processor configured to:
receive at a processor a first indication that a preemption of a first thread is desired in order to execute a second thread;
in response to receiving the first indication, wait for the first thread to reach a thread safe point, the thread safe point being a point in code at which if the first thread were to stop at the thread safe point, an operation that a third thread may want to perform on the first thread can be performed, wherein the first thread, the second thread and the third thread are different threads;
in the event that the first thread reaches a thread safe point, context switch the first thread out at the thread safe point and context switching the second thread in;
in the event that the first thread has not reached a thread safe point and it is detected that a second indication has been received, in response to the detection, preemptively context switch the first thread out and context switch the second thread in; and
in the case of a single processor system, in the event that a fourth thread requests that all other threads be at a safe point, and each of the other threads has already entered a thread safe point, begin executing the fourth thread immediately; and
a memory coupled with the processor, wherein the memory provides the processor with instructions.
38. A computer program product for preempting the execution of a thread, the computer program product being embodied in a non-transitory computer readable medium and comprising computer instructions for:
receiving at a processor a first indication that a preemption of a first thread is desired in order to execute a second thread;
in response to receiving the first indication, waiting for the first thread to reach a thread safe point, the thread safe point being a point in code at which if the first thread were to stop at the thread safe point, an operation that a third thread may want to perform on the first thread can be performed, wherein the first thread, the second thread and the third thread are different threads;
in the event that the first thread reaches a thread safe point, context switching the first thread out at the thread safe point and context switching the second thread in;
in the event that the first thread has not reached a thread safe point and it is detected that a second indication has been received, in response to the detection, preemptively context switching the first thread out and context switching the second thread in; and
in the case of a single processor system, in the event that a fourth thread requests that all other threads be at a safe point, and each of the other threads has already entered a thread safe point, begin executing the fourth thread immediately.