Nonvolatile semiconductor storage device
View Patent ↗A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.
1. A nonvolatile semiconductor memory device comprising:
a memory cell including first and second diffusion layers, a charge-storage portion between the first and second diffusion layers, a gate between the charge-storage portion and the first diffusion layer, and a word line formed above the charge storage portion and controlled separately from the gate;
and
a bit line connected to the memory cell;
wherein the charge storage portion is injected with hot electrons which are generated by passing charges accumulated in stray capacitance of the bit line through the memory cell at a portion in a semiconductor substrate under a boundary between the charge-storage portion and the gate when the memory cell is programmed or erased.
2. A nonvolatile semiconductor memory device according to claim 1 ,
wherein the charge storage portion is a floating gate.
3. A nonvolatile semiconductor memory device according to claim 1 ,
wherein the charge storage portion is a silicon nitride film.
4. A nonvolatile semiconductor memory device according to claim 1 ,
wherein a portion of the stray capacitance is formed of p-n junction capacitance of a diffusion layer of the memory cell.
5. A nonvolatile semiconductor memory device according to claim 1 , further comprising:
an internal power source circuit to generate a voltage to be applied to the bit line,
wherein, when the memory cell is programmed or erased, the internal power source circuit is brought to an inactive state.
6. A nonvolatile semiconductor memory device according to claim 1 ,
wherein, after the programming or the erase is performed a plurality of times, an operation of verifying a threshold voltage of the memory cell is performed.
7. A nonvolatile semiconductor memory device according to claim 6 ,
wherein the number of repeating the programming or the erase is incremented every time the threshold voltage verification operation is performed.
8. A nonvolatile semiconductor memory device comprising:
a memory cell including first and second diffusion layers, a charge-storage portion between the first and second diffusion layers, a gate between the charge-storage portion and the first diffusion layer, and a word line formed above the charge-storage portion and controlled separately from the gate;
and
a bit line connected to the memory cell;
means for injecting hot electrons into the charge-storage portion of the memory cell, which hot electrons are generated by passing charges accumulated in stray capacitance of the bit line through the memory cell at a portion in a semiconductor substrate under a boundary between the charge-storage portion and the gate, when the memory cell is programmed or erased.
9. A nonvolatile semiconductor memory device according to claim 8 ,
wherein the charge-storage portion is a floating gate.
10. A nonvolatile semiconductor memory device according to claim 8 ,
wherein the charge-storage portion is a silicon nitride film.
11. A nonvolatile semiconductor memory device according to claim 8 ,
wherein a portion of the stray capacitance is formed of p-n junction capacitance of a diffusion layer of the memory cell.
12. A nonvolatile semiconductor memory device according to claim 8 , further comprising:
an internal power source circuit to generate a voltage to be applied to the bit line,
wherein, when the memory cell is programmed or erased, the internal power source circuit is brought to an inactive state.
13. A nonvolatile semiconductor memory device according to claim 8 ,
wherein, after the programming or the erase is performed a plurality of times, an operation of verifying a threshold voltage of the memory cell is performed.
14. A nonvolatile semiconductor memory device according to claim 13 ,
wherein the number of repeating the programming or the erase is incremented every time the threshold voltage verification operation is performed.