Thin film transistor array panel including layered line structure and method for manufacturing the same
View Patent ↗The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).
1. A thin film transistor array panel comprising:
an insulating substrate;
a gate line formed on the insulating substrate;
a gate insulating layer formed on the gate line;
a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and
a pixel electrode coupled to the drain electrode,
wherein at least one of the gate line, the data line, and the drain electrode comprises a first layer comprising a conductive oxide, a second layer formed on the first layer and comprising copper (Cu), and a third layer formed on the second layer and comprising a conductive oxide, and the second layer is thicker than the first layer,
wherein the first layer or the third layer is an amorphous oxide.
2. The thin film transistor array panel of claim 1 , wherein the first layer comprises at least one of a-ITO, a-ITON, a-IZO, and a-IZON.
3. The thin film transistor array panel of claim 1 , wherein the third layer comprises at least one of a-ITO, a-ITON, a-IZO, and a-TZON.
4. The thin film transistor array panel of claim 1 , wherein the first layer and the third layer each comprises at least one of a-ITO, a-ITON, a-IZO, and a-IZON.
5. A thin film transistor array panel comprising:
an insulating substrate;
a gate line formed on the insulating substrate;
a gate insulating layer formed on the gate line;
a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and
a pixel electrode coupled to the drain electrode,
wherein at least one of the gate line, the data line, and the drain electrode comprises a first layer comprising IZO, IZON, or an amorphous conductive oxide and a second layer comprising copper (Cu), and
the second layer is disposed on or under the first layer and is thicker than the first layer.
6. The thin film transistor array panel of claim 5 , wherein the amorphous conductive oxide is a-ITO or a-ITON.
7. The thin film transistor array panel of claim 5 , further comprising a third layer facing the first layer with reference to the second layer.
8. The thin film transistor array panel of claim 7 , wherein the third layer comprises ITO, IZO, ITON, IZON, or an amorphous conductive oxide.
9. The thin film transistor array panel of claim 8 , wherein the amorphous conductive oxide is a-ITO or a-ITON.