Circuit and method for bias voltage generation

1. A bias voltage generation circuit for a phase interpolator, the bias voltage generation circuit comprising:

a voltage-to-current translation circuit configured to generate a first current that is positively related to a first voltage;

a current mirror circuit configured to generate a first bias voltage that is negatively related to the first current, and configured to generate a second current that is positively related to the first current;

a current-to-voltage translation circuit configured to generate a second bias voltage that is positively related to the second current; and

a resistive load circuit configured to provide a resistance coupled with an output clock signal of the phase interpolator;

wherein the first bias voltage controls the resistive load circuit; and

wherein the second bias voltage controls a current weighting circuit of the phase interpolator.

2. The bias voltage generation circuit of claim 1 , wherein the resistance is positively related to the first bias voltage.

3. The bias voltage generation circuit of claim 1 , wherein the current mirror circuit and the current-to-voltage translation circuit are physically located closer to the phase interpolator than is the voltage-to-current translation circuit.

4. The bias voltage generation circuit of claim 1 , wherein a magnitude of the second current is equal to a magnitude of the first current.

5. The bias voltage generation circuit of claim 1 , wherein a magnitude of the second bias voltage is equal to a magnitude of the first voltage.

6. The bias voltage generation circuit of claim 1 , wherein the first voltage is a bias control signal of a voltage-controlled oscillator.

7. The bias voltage generation circuit of claim 1 , the voltage-to-current translation circuit comprising:

an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) comprising a gate coupled with the first voltage, a drain coupled with the current mirror circuit, and a source coupled with a voltage reference.

8. The bias voltage generation circuit of claim 1 , the current mirror circuit comprising:

a first p-channel MOSFET comprising a gate and a drain coupled with the voltage-to-current translation circuit, and a source coupled with a drain voltage; and

a second p-channel MOSFET comprising a gate coupled with the gate of the first p-channel MOSFET, and a source coupled with the drain voltage;

wherein the drain of the first p-channel MOSFET produces the first bias voltage.

9. The bias voltage generation circuit of claim 1 , the current-to-voltage translation circuit comprising:

an n-channel MOSFET comprising a gate and a drain coupled with the current mirror circuit, and a source coupled with a voltage reference;

wherein the gate and the drain produce the second bias voltage.

10. The bias voltage generation circuit of claim 1 , the resistive load circuit comprising:

a first p-channel MOSFET comprising a gate and a drain coupled with the output, and a source coupled with a drain voltage; and

a second p-channel MOSFET comprising a gate driven by the first bias voltage, a drain coupled the drain of the first p-channel MOSFET and a source coupled with the drain voltage.

11. The bias voltage generation circuit of claim 1 , further comprising the phase interpolator.

12. A phase generator comprising the bias voltage generation circuit of claim 11 .

13. A method of generating a first and second bias voltages for a phase interpolator, comprising:

providing a first current that is positively related to a first voltage;

generating the first bias voltage, the first bias voltage being negatively related to the first current;

applying a resistance to an output clock signal of the phase interpolator, wherein the resistance is controlled via the first bias voltage;

mirroring the first current to yield a second current;

producing the second bias voltage, the second bias voltage being positively related to the second current; and

controlling a current weighting circuit of the phase interpolator via the second bias voltage.

14. The method of claim 13 , wherein the resistance is positively related to the first bias voltage.

15. The method of claim 13 , wherein a magnitude of the second current is equal to a magnitude of the first current.

16. The method of claim 13 , wherein a magnitude of the second bias voltage is equal to a magnitude off the first voltage.

17. The method of claim 13 , wherein the first voltage is a bias control signal or a voltage-controlled oscillator.

18. A phase interpolator employing the method of claim 13 .

19. A phase generator comprising the phase interpolator of claim 18 .

20. A bias voltage generation circuit for a phase interpolator, the bias voltage generation circuit comprising:

means for providing a first current positively related to a first voltage;

means for creating a second current positively related to the first current, the creating means also yielding a first bias voltage which is negatively related to the first current;

a resistance coupled with an output clock signal of the phase interpolator, wherein the resistance is controlled by the first bias voltage; and

means for producing a second bias voltage which is positively related to the second current, wherein the second bias voltage controls a current weighting circuit of the phase interpolator.

21. The bias voltage generation circuit of claim 20 , wherein the resistance is positively related to the first bias voltage.

22. The bias voltage generation circuit of claim 20 , wherein a magnitude of the second current is equal to a magnitude of the first current.

23. The bias voltage generation circuit of claim 20 , wherein a magnitude of the second bias voltage is equal to a magnitude of the first voltage.

24. The bias voltage generation circuit of claim 20 , wherein the first voltage is a bias control signal of a voltage-controlled oscillator.

25. The bias voltage generation circuit of claim 20 , further comprising the phase interpolator.

26. A phase generator comprising the bias voltage generation circuit of claim 25 .