Printer controller for a pagewidth printhead
View Patent ↗A printer controller for a pagewidth printer includes input interface circuitry configured to receive page description data in the form of bi-level data and contone data. Decompression circuitry is configured to decompress, in parallel processes, the bi-level data and the contone data. Halftoning circuitry receives and halftones the decompressed contone data. Compositing circuitry receives and composites the bi-level data. Printhead interface circuitry is configured to provide a pagewidth printhead with print data generated by the combined operation of the halftoning and compositing circuitry.
1. A printer controller for a pagewidth printer, the printer controller comprising:
input interface circuitry configured to receive page description data in the form of bi-level data and contone data;
decompression circuitry configured to decompress, in parallel processes, the bi-level data and the contone data;
halftoning circuitry for receiving and halftoning the decompressed contone data;
compositing circuitry for receiving and compositing the bi-level data; and
printhead interface circuitry configured to provide a pagewidth printhead with print data generated by the combined operation of the halftoning and compositing circuitry.
2. A printer controller as claimed in claim 1 , in which the input interface circuitry defines a universal serial bus interface to permit the printer controller to be connected to a computer in a conventional manner.
3. A printer controller as claimed in claim 1 , in which the decompression circuitry defines an EDRL expander configured to expand the bi-level data and a JPEG decoder configured to expand the contone data.
4. A printer controller as claimed in claim 1 , in which the halftoning circuitry and the compositor circuitry define a halftoner and compositer unit such that the halftoning and compositing processes are carried out substantially simultaneously and in parallel.
5. A printer controller as claimed in claim 1 , which includes a central processor having a bus, the input interface circuitry, the printhead interface circuitry, the decompression circuitry, the halftoning circuitry and the compositing circuitry all being connected to the bus to facilitate communication.
6. A printer controller as claimed in claim 5 , which includes processing circuitry connected to the bus and configured to control operation and interaction of the components of the printer controller.
7. A printer controller as claimed in claim 5 , which includes a memory connected to the bus for storing and buffering compressed page description data and print data.
8. A printer controller as claimed in claim 7 , which includes DMA controller circuitry connected to the bus and configured to control writing to and reading from the memory.