CMOS solid-state imaging device and method of manufacturing the same as well as drive method of CMOS solid-state imaging device
View Patent ↗A CMOS solid-state imaging device configured to restrain the occurrence of white spots and dark current caused by pixel defects, and also to increase the saturation signal amount. Adjacent pixels are separated by an element isolation portion formed of a diffusion layer and an insulating layer thereon, and the insulating layer of the element isolation portion is formed in a position equal to or shallower than the position of a pn junction on the side of an accumulation layer of a photoelectric conversion portion 38 constituting a pixel.
1. A CMOS solid-state imaging device comprising:
a silicon substrate;
a plurality of pixels, each of which includes a photoelectric conversion portion;
an element isolation portion including a diffusion layer and a first insulating layer thereon; and
a second insulating layer on a surface of the silicon substrate,
wherein,
adjacent ones of said plurality of pixels are separated by the element isolation portion, and
a charge-accumulation region of said photoelectric conversion portion in each of the plurality of pixels extends under the second insulating layer.
2. A CMOS solid-state imaging device comprising:
a plurality of pixels each of which includes a photoelectric conversion portion,
wherein,
adjacent ones of said plurality of pixels are separated by an element isolation portion formed of a diffusion layer and an insulating layer thereon, and
the diffusion layer of said element isolation portion at least has surface concentration equal to or higher than that of an accumulation layer of said photoelectric conversion portion.
3. A CMOS solid-state imaging device comprising:
a plurality of pixels each of which includes a photoelectric conversion portion,
wherein,
adjacent ones of said plurality of pixels are separated by an element isolation portion formed of a diffusion layer and an insulating layer thereon, and
a surface concentration of said diffusion layer, at least under an area where a gate electrode extends over said insulating layer, is at least higher than a concentration of an accumulation layer of said photoelectric conversion portion.
4. A CMOS solid-state imaging device according to claim 2 , wherein an impurity concentration of said diffusion layer of said element isolation portion is gradually lowered in a depth direction.
5. A CMOS solid-state imaging device according to any of claims 1 , 2 and 3 wherein said first insulating layer of said element isolation portion is formed in a position equal to the depth of a pn junction including an accumulation layer of a photoelectric conversion portion in each of said plurality of pixels, or in a position shallower than the depth of said pn junction.
6. A CMOS solid-state imaging device according to any of claims 1 , 2 and 3 , wherein said first insulating layer of said element isolation portion is formed in a depth corresponding to a position between a surface of a semiconductor body in which said plurality of pixels are formed and a pn junction of said photoelectric conversion portion.
7. A CMOS solid-state imaging device according to any of claims 1 , 2 and 3 ,
wherein,
each pixel includes a source/drain region, and
the photoelectric conversion element in a first pixel included in said plurality of pixels and the source/drain region of a transistor in a second pixel adjacent to said first pixel are separated from each other by an element isolation portion formed of a diffusion layer and an insulating layer thereon and wherein said source/drain region is formed apart from said diffusion layer.