Bottom gate thin film transistor, flat panel display having the same and method of fabricating the same

1. A thin film transistor (TFT) comprising:

a gate electrode disposed on a substrate;

a gate insulating layer disposed on the gate electrode;

a semiconductor layer disposed on the gate insulating layer and crossing over the gate electrode, wherein the semiconductor layer is crystallized by a metal induced lateral crystallization (MILC) technique;

an inter-insulating layer disposed on the semiconductor layer and comprising source and drain contact holes that expose portions of the semiconductor layer, wherein at least one edge of each of the source and drain contact holes of the inter-insulating layer overlaps the gate electrode; and

source and drain electrodes disposed on the exposed portions of the semiconductor layer in the source and drain contact holes, respectively,

wherein the semiconductor layer comprises metal induced crystallization (MIC) regions corresponding to the exposed portions of the semiconductor layer in the source and drain contact holes.

2. The TFT of claim 1 , wherein the source and drain electrodes directly contact the exposed portions of the semiconductor layer.

3. The TFT of claim 1 , wherein edges of the source and drain contact holes are separated from all edges of the semiconductor layer crossing over the gate electrode by a minimum distance.

4. The TFT of claim 1 , wherein the minimum distance between the edges of the source and drain contact holes and the edge of the semiconductor layer crossing over the gate electrode is in a range of about 0.5 μm to about 10 μm.

5. The TFT of claim 1 , wherein the inter-insulating layer has a thickness of about 1000 to 5000 Å.

6. The TFT of claim 1 , wherein the semiconductor layer crosses over the gate electrode in a substantially orthogonal configuration.

7. A thin film transistor (TFT) comprising:

a gate electrode disposed on a substrate;

a gate insulating layer disposed on the gate electrode;

a semiconductor layer disposed on the gate insulating layer and crossing over the gate electrode;

an inter-insulating layer disposed on the semiconductor layer and comprising source and drain contact holes formed therein and exposing portions of the semiconductor layer, wherein at least one edge of each of the source and drain contact holes of the inter-insulating layer overlaps the gate electrode; and

source and drain electrodes disposed on the exposed portions of the semiconductor layer,

wherein the semiconductor layer comprises conductive regions corresponding to the exposed portions of the semiconductor layer in the source and drain contact holes.

8. The TFT of claim 7 , wherein the semiconductor layer comprises a metal induced crystallization (MIC) region and a metal induced lateral crystallization (MILC) region and is crystallized by an MILC technique.

9. The TFT of claim 8 , wherein the MIC region corresponds to the exposed portions of the semiconductor layer in the source and drain contact holes.

10. The TFT of claim 7 , wherein the source and drain electrodes directly contact the exposed portions of the semiconductor layer.

11. The TFT of claim 7 , wherein the edges of the source and drain contact holes are separated from all edges of the semiconductor layer crossing over the gate electrode among all the edges of the semiconductor layer.

12. The TFT of claim 7 , wherein the semiconductor layer crosses over the gate electrode in a substantially orthogonal configuration.