Thin film transistor, method of manufacturing the same, display apparatus having the same and method of manufacturing the display apparatus
View Patent ↗A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the substrate, a channel pattern, a source electrode and a drain electrode. The channel pattern includes a semiconductor pattern formed on the gate electrode and overlaying the gate electrode as well as first and second conductive adhesive patterns formed on the semiconductor pattern and spaced apart from each other. The source electrode includes a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern. The drain electrode includes a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern. Etched portions of the first and second conductive adhesive patterns have a substantially vertical profile to prevent the exposure of the source and drain electrodes, thereby improving the characteristics of the thin film transistor.
1. A thin film transistor comprising:
a gate electrode on a substrate;
a gate insulating layer on the substrate to insulate the gate electrode;
a channel pattern including:
a semiconductor pattern on the gate electrode such that the semiconductor pattern overlays the gate electrode;
a first conductive adhesive pattern on the semiconductor pattern; and
a second conductive adhesive pattern formed on the semiconductor pattern and spaced apart from the first conductive adhesive pattern;
a source electrode having a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern; and
a drain electrode having a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern;
wherein each of end portions of the first capping pattern, the second capping pattern, the source pattern and the drain pattern comprises a tapered structure;
the source and the drain patterns comprise a metal selected from the group consisting of aluminum, an aluminum alloy, copper, and a copper alloy; and
the first and second barrier patterns comprise a metal different from that of the first and second capping patterns.
2. The thin film transistor of claim 1 , wherein the first and second barrier patterns comprise a metal selected from the group consisting of titanium, tantalum, tungsten and chromium.
3. The thin film transistor of claim 1 , wherein the first and second capping patterns comprise a metal selected from the group consisting of molybdenum and a molybdenum alloy.
4. The thin film transistor of claim 3 , wherein the molybdenum alloy comprises molybdenum-niobium.
5. The thin film transistor of claim 1 , wherein an end portion of the first barrier pattern and an end portion of the second barrier pattern facing the end portion of the first barrier pattern comprise a substantially vertical profile, and
an end portion of the first conductive adhesive pattern and an end portion of the second conductive adhesive pattern facing the end portion of the first conductive adhesive pattern comprise a substantially vertical profile.
6. The thin film transistor of claim 1 , wherein the semiconductor pattern comprises a recess corresponding to the gate electrode.
7. The thin film transistor of claim 6 , wherein the first and second conductive adhesive patterns are disposed on two sides of the recess, respectively.
8. A display apparatus comprising:
a first display substrate which includes:
a thin film transistor that has:
a gate electrode on a first substrate;
a gate insulating layer on the first substrate to insulate the gate electrode;
a channel pattern having a semiconductor pattern on the gate electrode such that the semiconductor pattern overlays the gate electrode, a first conductive adhesive pattern on the semiconductor pattern, and a second conductive adhesive pattern spaced apart from the first conductive adhesive pattern on the semiconductor pattern;
a source electrode having a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern;
a drain electrode having a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern; and
a pixel electrode electrically connected to the drain electrode;
wherein the source and the drain patterns comprise a metal selected from the group consisting of aluminum and an aluminum alloy; and
the first and second barrier patterns comprise a metal different from that of the first and second capping patterns;
a second display substrate having a second substrate facing the first substrate, and a common electrode facing the pixel electrode; and
a liquid crystal layer between the first and second display substrates.
9. The display apparatus of claim 8 , wherein the first and second barrier patterns comprise a metal selected from the group consisting of titanium, tantalum, tungsten and chromium.
10. The display apparatus of claim 8 , wherein the first and second capping patterns comprise a metal selected from the group consisting of molybdenum and molybdenum alloy.